diff options
author | Tom Rini <trini@konsulko.com> | 2017-02-03 20:33:42 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2017-02-03 20:33:42 -0500 |
commit | c83a824e62277162ad35f52879b2316902c0eff5 (patch) | |
tree | fa91cdcda24b8822d0f1e52786b2657e4d68be27 /include | |
parent | 0ff27d4a94637d4b1937c625d33212375bd118d9 (diff) | |
parent | add63f94a9c3bbe1af3fdf3f4c56a5185a4c0504 (diff) |
Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
configs/ls1046aqds_defconfig
configs/ls1046aqds_nand_defconfig
configs/ls1046aqds_qspi_defconfig
configs/ls1046aqds_sdcard_ifc_defconfig
configs/ls1046aqds_sdcard_qspi_defconfig
configs/ls1046ardb_emmc_defconfig
configs/ls1046ardb_qspi_defconfig
configs/ls1046ardb_sdcard_defconfig
Diffstat (limited to 'include')
30 files changed, 13 insertions, 29 deletions
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index fc99b965a3c..2fdb869383c 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -63,7 +63,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 77f0927d6e5..41162349cf1 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -46,7 +46,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_TSEC_ENET diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 9e729fd2f74..942123b8288 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index e1ce7ad55b7..8f68748d876 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 4635cdfcde0..b9eab4e382e 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif -#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index caa52bec00d..91e17d93994 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ - #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index b933d21d4b7..3d4c8a81024 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -28,7 +28,6 @@ /* High Level Configuration Options */ #define CONFIG_MP 1 /* support multiple processors */ -#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index baa83698c50..cf574da7c33 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -130,7 +130,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index f1d8116fb25..e601cc64bd1 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -96,7 +96,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 1369035c6bd..58a3507dc17 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -25,7 +25,6 @@ /* High Level Configuration Options */ #define CONFIG_MP /* support multiple processors */ -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 15384f1e879..3fad88f62c8 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -41,7 +41,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 00ffb835390..fcaa803c4e8 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 02c3fddf2f0..e46bf007adb 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index bd8e46e9422..2d436c2900c 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 82d3f102e55..9306b734081 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -162,7 +162,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a9835b9317e..0a65d0e8648 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -33,7 +33,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 1e2b94e74f1..f8337320387 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2a1b547ae1c..dbb9fd4da1d 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -73,7 +73,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 28f4b148b22..8082ec5d7c6 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -14,7 +14,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_FSL_ELBC #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index e5d60fbf3c0..cc2b2736f48 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -137,7 +137,6 @@ /* * Local Bus Definitions */ -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_SYS_ELBC_BASE 0xe0000000 #ifdef CONFIG_PHYS_64BIT diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7637bb8777c..dd38fa3511e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -59,7 +59,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index c9a57afbaea..3f195ab4135 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 8669fcd4313..efd3b289002 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -35,7 +35,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 81f8d6263e5..0965afafb14 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -29,6 +29,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL /* Generic Timer Definitions */ #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index efc0fd936e0..0e648b1ac88 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -135,6 +135,18 @@ unsigned long get_board_ddr_clk(void); #define CFG_LPUART_EN 0x2 #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_HCD +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9b142bc6f47..88876d639e5 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -260,7 +260,6 @@ #define CONFIG_MP -#define CONFIG_FSL_ELBC #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index a98e1b2b17f..d403f846177 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -40,7 +40,6 @@ #define CONFIG_MP -#define CONFIG_FSL_ELBC #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 15c0e8935cc..7803a849bc1 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 5d78560f3ee..2f133d2b6ed 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -29,7 +29,6 @@ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_FSL_ELBC 1 /* * Multicore config diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 6346f849d46..4ac25a6b214 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -30,7 +30,6 @@ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_FSL_ELBC 1 /* * Multicore config |