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authorClemens Gruber <clemens.gruber@pqgruber.com>2018-01-07 20:26:29 +0100
committerTom Rini <trini@konsulko.com>2018-01-08 08:26:03 -0500
commit598e9dccc75d8302df58560c52487248a6c33c4d (patch)
tree805e773b33c458ab20982405eb3b180623d89419 /include
parentca833ca9579b29c5667ea2fa7a9d3f89f1599a94 (diff)
crypto/fsl: fix BLOB encapsulation and decapsulation
The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command" To ensure coherency, we require the key_mod, src and dst buffers to be aligned to the cache line size and flush/invalidate the memory regions. The same requirements apply to the job descriptor. Tested on an i.MX6Q board. Reviewed-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
Diffstat (limited to 'include')
-rw-r--r--include/fsl_sec.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 61c671d6c7..a2f5f5a5f1 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -215,6 +215,8 @@ struct sg_entry {
#define SG_ENTRY_OFFSET_SHIFT 0
};
+#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
+
#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
/* Job Ring Base Address */
#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
@@ -274,8 +276,6 @@ struct sg_entry {
#define PERM 0x0000B008 /* Clear on release, lock SMAP
* lock SMAG group 1 Blob */
-#define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */
-
/* HAB WRAPPED KEY header */
#define WRP_HDR_SIZE 0x08
#define HDR_TAG 0x81