diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2011-10-12 14:06:56 -0700 |
|---|---|---|
| committer | Vadim Bendebury <vbendeb@chromium.org> | 2011-10-12 16:37:20 -0700 |
| commit | b0c9145b37fea4f760a38dd64ff5f14a1b28b894 (patch) | |
| tree | 2de69e7d0687a5b09aeb2d17540acbcdfdd36fb6 /include | |
| parent | 217decb37c0a7904f08452a82285d44f98ecbb41 (diff) | |
[PATCH2/2] mrc cache: Handle MRC cache data.
This change adds a chromebook-x86 platform specific initialization
which does the following:
- find MRC cache in the SPI flash using the FMAP data
- compare the cache contents passed by coreboot through CBMEM with
the contents saved in the SPI flash
- if the two do not match and the new contents would fit into the
FMAP allocated room - update the contents in the SPI flash.
BUG=chrome-os-partner:5808
TEST=manual
. build the new firmware image
. place the updated coreboot/util/cbmem/cbmem.py utility into /var
on a Stumpy (the target) configured for ssh communications
. program the new image on the target
. reboot the target and wait for it to come up to ChromeOS login screen
. run the following from the host:
(host) ssh 172.22.75.233 egrep "'(handle|prepare)_mrc'" /sys/firmware/log
prepare_mrc_cache: MRC cache not initialized?
handle_mrc_cache: cached storage mismatch (-1/2899)
(host) ssh 172.22.75.233 /var/cbmem.py| grep -A1 'time base'
time base 2194240, total entries 3
1:79,373 2:765,726 1000:1,429,038
. reboot the target and repeat the commands once it comes up
(host) ssh 172.22.75.233 /var/cbmem.py| grep -A1 'time base'
time base 2124288, total entries 3
1:48,707 2:112,177 1000:754,652
(host) ssh 172.22.75.233 egrep "'(handle|prepare)_mrc'" /sys/firmware/log
prepare_mrc_cache: at ffbff004, size b53
handle_mrc_cache: cached storage match
Observe that during first startup u-boot detects the MRC cache
mismatch (and presumably saves the new copy). During the second
startup coreboot finds the saved MRC cache blob, and u-boot reports
that the CBMEM and SPI instances are the same.
Also, observe much lower timestamp values on the second run.
Change-Id: I4ab11f9281a7eec777e98fe7a8fd1e0f6abfd859
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/9981
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/coreboot.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index f23223b59d..0e004fccae 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -295,6 +295,9 @@ #define CONFIG_CMD_USB #undef CONFIG_CMD_XIMG +/* Board specific late time init */ +#define CONFIG_MISC_INIT_R + /* Boot options */ #define CONFIG_BOOTDELAY 0 /* -1 to disable auto boot */ |