Merge git://git.denx.de/u-boot-fsl-qoriq

9 files changed, 9 insertions, 14 deletions

diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 0df90161d75..ea48421bbeb 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -148,7 +148,6 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(512UL * 1024 * 1024)
 #endif
 /* Command line configuration */
-#define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_CACHE
 
 /* Miscellaneous configurable options */
@@ -195,10 +194,6 @@ unsigned long long get_qixis_addr(void);
 	"mcinitcmd=fsl_mc start mc 0x580a00000"	\
 	" 0x580e00000 \0"
 
-#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
-				"earlycon=uart8250,mmio,0x21c0500 " \
-				"ramdisk_size=0x3000000 default_hugepagesz=2m" \
-				" hugepagesz=2m hugepages=256"
 #if defined(CONFIG_QSPI_BOOT)
 #define CONFIG_BOOTCOMMAND	"sf probe 0:0;" \
 				"sf read 0x80200000 0xd00000 0x100000;"\
diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h
index 8d7c14d97db..2278ac952ea 100644
--- a/include/fsl-mc/fsl_dpbp.h
+++ b/include/fsl-mc/fsl_dpbp.h
@@ -2,7 +2,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 /*!
diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h
index c300c94e202..7788e1962e6 100644
--- a/include/fsl-mc/fsl_dpio.h
+++ b/include/fsl-mc/fsl_dpio.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 
diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h
index 66cf3bf6a21..1cea123a316 100644
--- a/include/fsl-mc/fsl_dpmac.h
+++ b/include/fsl-mc/fsl_dpmac.h
@@ -2,7 +2,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
  */
diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h
index 309d323acf7..96d81d99349 100644
--- a/include/fsl-mc/fsl_dpni.h
+++ b/include/fsl-mc/fsl_dpni.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 #ifndef _FSL_DPNI_H
diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h
index 779d6f95672..950ecb07569 100644
--- a/include/fsl-mc/fsl_dprc.h
+++ b/include/fsl-mc/fsl_dprc.h
@@ -2,7 +2,7 @@
 /*
  * Freescale Layerscape MC I/O wrapper
  *
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 #ifndef _FSL_DPRC_H
diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h
index 179f6698283..591cda96851 100644
--- a/include/fsl-mc/fsl_mc_cmd.h
+++ b/include/fsl-mc/fsl_mc_cmd.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+/* Copyright 2013-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 #ifndef __FSL_MC_CMD_H
diff --git a/include/fsl-mc/fsl_mc_private.h b/include/fsl-mc/fsl_mc_private.h
index f4b5a99e15d..ba0bc379d5b 100644
--- a/include/fsl-mc/fsl_mc_private.h
+++ b/include/fsl-mc/fsl_mc_private.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  */
 
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index d051e92ce4c..8120ca0de86 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -891,8 +891,8 @@ struct fsl_ifc_nand {
 	u32 nand_erattr1;
 	u32 res19[0x10];
 	u32 nand_fsr;
-	u32 res20[0x3];
-	u32 nand_eccstat[6];
+	u32 res20[0x1];
+	u32 nand_eccstat[8];
 	u32 res21[0x1c];
 	u32 nanndcr;
 	u32 res22[0x2];