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authorMinghuan Lian <Minghuan.Lian@nxp.com>2016-12-13 14:54:18 +0800
committerYork Sun <york.sun@nxp.com>2017-01-18 09:26:47 -0800
commit8808aeb7a93dc36973f3a421e00d8e32318b0352 (patch)
tree4ee870ba6e8faa710442873fe906060e7e7e0230 /include
parent80afc63fc34286d363074d7779322c8720f346b5 (diff)
arm: ls1021a: Enable PCIe in defconfigs
The patch enables PCIe in ls1021a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/ls1021aiot.h19
-rw-r--r--include/configs/ls1021aqds.h16
-rw-r--r--include/configs/ls1021atwr.h16
3 files changed, 0 insertions, 51 deletions
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index ae8ee2412fc..e270f426ffa 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -232,31 +232,12 @@
#endif
/* PCIe */
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 */
#define CONFIG_PCIE2 /* PCIE controler 2 */
-/* Use common FSL Layerscape PCIe code */
-#define CONFIG_PCIE_LAYERSCAPE
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
-
#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 6f857a75ad4..f1d197592ba 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -500,24 +500,8 @@ unsigned long get_board_ddr_clk(void);
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index b48cd0062be..6aff6b5276b 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -370,24 +370,8 @@
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI