diff options
| author | Stefan Roese <sr@denx.de> | 2007-10-15 11:29:33 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-10-15 11:29:33 +0200 |
| commit | 5a5958b7de70ae99f0e7cbd5c97ec1346e051587 (patch) | |
| tree | 3f3830d2dfc19992bc1631c090d2a46d89cc989e /include | |
| parent | f8bf90461d9bad2e6fed31fcebaf235f60dd6763 (diff) | |
ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite
The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.
This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/sequoia.h | 2 | ||||
| -rw-r--r-- | include/configs/yosemite.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index c2e1386217f..600f98cf0d4 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -450,6 +450,8 @@ #define CFG_EBC_PB2AP 0x24814580 #define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000) +#define CFG_BCSR5_PCI66EN 0x80 + /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 6a5b7f1eaac..35bce4af904 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -359,6 +359,8 @@ #define CFG_EBC_PB2AP 0x04814500 #define CFG_EBC_PB2CR (CFG_CPLD | 0x18000) +#define CFG_BCSR5_PCI66EN 0x80 + /*----------------------------------------------------------------------- * Cache Configuration */ |