Freescale board patch for MPC5125_TWR board

10 files changed, 1495 insertions, 86 deletions

diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index e5a3b2c170a..476419a8b87 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -92,7 +92,7 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	u32 lbc_clk;
 #endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
-#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) ||defined(CONFIG_ADS5125)
 	u32 i2c1_clk;
 	u32 i2c2_clk;
 #endif
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index 808786985e5..8e341b9bb6b 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -76,7 +76,10 @@ typedef struct wdt512x {
  * RTC Module Registers
  */
 typedef struct rtclk512x {
-	u8 fixme[0x100];
+	u8 fixme[0x24];
+	u32 atr;
+	u32 kar;
+	u8 fixme1[0xD4];
 } rtclk512x_t;
 
 /*
@@ -387,7 +390,7 @@ typedef struct fec512x {
  * ULPI
  */
 typedef struct ulpi512x {
-	u8 fixme[0x600];
+	u8 fixme[0x400];
 } ulpi512x_t;
 
 /*
@@ -408,7 +411,11 @@ typedef struct pcidma512x {
  * IO Control
  */
 typedef struct ioctrl512x {
+#ifdef CONFIG_ADS5125
+	u8 regs[0x1000];
+#else
 	u32 regs[0x400];
+#endif
 } ioctrl512x_t;
 
 /*
@@ -503,7 +510,54 @@ typedef struct pata512x {
  * PSC
  */
 typedef struct psc512x {
+#ifdef CONFIG_ADS5125
+	volatile u8	mr1;		/* PSC + 0x00 */
+	volatile u8	res0[3];
+	volatile u8	mr2;		/* PSC + 0x04 */
+	volatile u8	res0a[3];
+	volatile u16	psc_status;	/* PSC + 0x08 */
+	volatile u16	res1;
+	volatile u16	psc_clock_select;/* PSC + 0x0C mpc5125 manual has this as u8       */
+					 /* it has u8 res after it and for compatibility   */
+					 /* will keep u16 so high bits are set as before   */
+	volatile u16	res1a;
+	volatile u8	command;	/* PSC + 0x10 */
+	volatile u8	res2[3];
+	union {				/* PSC + 0x14 */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} buffer;
+#define psc_buffer_8	buffer.buffer_8
+#define psc_buffer_16	buffer.buffer_16
+#define psc_buffer_32	buffer.buffer_32
+	volatile u8	psc_ipcr;	/* PSC + 0x18 */
+	volatile u8	res3[3];
+	volatile u8	psc_acr;	/* PSC + 0x1C */
+	volatile u8	res3a[3];
+	volatile u16	psc_isr;	/* PSC + 0x20 */
+	volatile u16	res4;
+	volatile u16	psc_imr;	/* PSC + 0x24 */
+	volatile u16	res4a;
+	volatile u8	ctur;		/* PSC + 0x28 */
+	volatile u8	res5[3];
+	volatile u8	ctlr;		/* PSC + 0x2c */
+	volatile u8	res6[3];
+	volatile u32	ccr;		/* PSC + 0x30 */
+	volatile u8	res7[12];
+	volatile u8	ivr;		/* PSC + 0x40 */
+	volatile u8	res8[3];
+	volatile u8	ip;		/* PSC + 0x44 */
+	volatile u8	res9[3];
+	volatile u8	op1;		/* PSC + 0x48 */
+	volatile u8	res10[3];
+	volatile u8	op0;		/* PSC + 0x4c */
+	volatile u8	res11[3];
+	volatile u32	sicr;		/* PSC + 0x50 */
+	volatile u8	res12[44];
+#else
 	volatile u8	mode;		/* PSC + 0x00 */
+					/* serves as both mr1 and mr2 (only mr1 on mpc5121 */
 	volatile u8	res0[3];
 	union {				/* PSC + 0x04 */
 		volatile u16	status;
@@ -537,7 +591,7 @@ typedef struct psc512x {
 #define psc_imr		isr_imr.imr
 	volatile u16	res4;
 	volatile u8	ctur;		/* PSC + 0x18 */
-	volatile u8	res5[3];
+	volatile u8	res5[3];/*28*/
 	volatile u8	ctlr;		/* PSC + 0x1c */
 	volatile u8	res6[3];
 	volatile u32	ccr;		/* PSC + 0x20 */
@@ -552,6 +606,7 @@ typedef struct psc512x {
 	volatile u8	res11[3];
 	volatile u32	sicr;		/* PSC + 0x40 */
 	volatile u8	res12[60];
+#endif /* FIFOC is the same for all mpc512x */
 	volatile u32	tfcmd;		/* PSC + 0x80 */
 	volatile u32	tfalarm;	/* PSC + 0x84 */
 	volatile u32	tfstat;		/* PSC + 0x88 */
@@ -561,8 +616,10 @@ typedef struct psc512x {
 	volatile u16	tfwptr;		/* PSC + 0x98 */
 	volatile u16	tfrptr;		/* PSC + 0x9A */
 	volatile u32	tfsize;		/* PSC + 0x9C */
+#ifndef ADS5125
 	volatile u8	res13[28];
-	union {				/* PSC + 0xBC */
+#endif
+	union {				/* PSC + 0xBC  */
 		volatile u8	buffer_8;
 		volatile u16	buffer_16;
 		volatile u32	buffer_32;
@@ -635,7 +692,15 @@ typedef struct immap {
 	u8			res3[0x500];
 	fec512x_t		fec;		/* Fast Ethernet Controller */
 	ulpi512x_t		ulpi;		/* USB ULPI */
-	u8			res4[0xa00];
+	u8			res4[0xc00];
+#ifdef CONFIG_ADS5125
+	ulpi512x_t		ulpi2;		/* USB ULPI */
+	u8			res5[0x400];
+	fec512x_t		fec2;		/* 2nd Fast Ethernet Controller */
+	gpt512x_t		gpt2;		/* 2nd General Purpose Timer */
+	sdhc512x_t		sdhc2;		/* 2nd SDHC */
+	u8			res6[0x3e00];
+#else
 	utmi512x_t		utmi;		/* USB UTMI */
 	u8			res5[0x1000];
 	pcidma512x_t		pci_dma;	/* PCI DMA */
@@ -644,6 +709,7 @@ typedef struct immap {
 	ios512x_t		ios;		/* PCI Sequencer */
 	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control and Status */
 	u8			res7[0xa00];
+#endif
 	ddr512x_t		mddrc;		/* Multi-port DDR Memory Controller */
 	ioctrl512x_t		io_ctrl;	/* IO Control */
 	iim512x_t		iim;		/* IC Identification module */
@@ -651,9 +717,14 @@ typedef struct immap {
 	lpc512x_t		lpc;		/* LocalPlus Controller */
 	pata512x_t		pata;		/* Parallel ATA */
 	u8			res9[0xd00];
+#ifdef CONFIG_ADS5125
+	psc512x_t		psc[10];	/* PSCs */
+	u8			res10[0x500];
+#else
 	psc512x_t		psc[12];	/* PSCs */
 	u8			res10[0x300];
-	fifoc512x_t		fifoc;		/* FIFO Controller */
+#endif
+	fifoc512x_t		fifoc;		/* FIFO Controller PSC +0xF00 */
 	u8			res11[0x2000];
 	dma512x_t		dma;		/* DMA */
 	u8			res12[0xa800];
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 8fda3f29fab..f326bfc2444 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -33,6 +33,7 @@
  *
  * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
  * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
+ * 0x4000_0000 - 0x400F_FFFF	NFC (1 MB)
  * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
  * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
  * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
@@ -65,6 +66,10 @@
 #define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
 #define CONFIG_PCI
 #endif
+/*
+ * Enable Fast boot
+ */
+#define CONFIG_FASTBOOT
 
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
 #define CONFIG_MISC_INIT_R
@@ -130,54 +135,65 @@
  *	[09:05]	DRAM tRP:
  *	[04:00] DRAM tRPA
  */
+#define MDDRC_SYS_CFG_RUN		~(0x10000000)
 #ifdef CONFIG_ADS5121_REV2
-#define CONFIG_SYS_MDDRC_SYS_CFG	0xF8604A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	0xE8604A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
+#define MDDRC_SYS_CFG_MICRON		0xF8604A00
+#define MDDRC_TIME_CFG1_MICRON		0x54EC1168
+#define MDDRC_TIME_CFG2_MICRON		0x35210864
 #else
-#define CONFIG_SYS_MDDRC_SYS_CFG	 0xFA804A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	 0xEA804A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
+#define MDDRC_SYS_CFG_MICRON	 	0xFA804A00
+#define MDDRC_SYS_CFG_MICRON_RUN	0xEA804A00
+#define MDDRC_TIME_CFG1_MICRON		0x68EC1168
+#define MDDRC_TIME_CFG2_MICRON		0x34310864
 #endif
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x06183D2E
-
-#define CONFIG_SYS_MICRON_NOP		0x01380000
-#define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
-#define CONFIG_SYS_MICRON_EM2		0x01020000
-#define CONFIG_SYS_MICRON_EM3		0x01030000
-#define CONFIG_SYS_MICRON_EN_DLL	0x01010000
-#define CONFIG_SYS_MICRON_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-#define CONFIG_SYS_MICRON_OCD_DEFAULT	0x01010780
+#define MDDRC_SYS_CFG_ELPIDA	 	0xFA802B00
+#define MDDRC_SYS_CFG_ELPIDA_RUN	0xEA802B00
+#define MDDRC_TIME_CFG1_ELPIDA		0x690e1189
+#define MDDRC_TIME_CFG2_ELPIDA		0x35310864
+#define MDDRC_TIME_CFG0			0x00003D2E
+#define MDDRC_TIME_CFG0_RUN		0x06183D2E
+#define MDDRC_SYS_CFG_EN		0xF0000000
+#define MDDRC_SYS_CFG_CLK_BIT		(1 << 29)
+#define MDDRC_SYS_CFG_CKE_BIT		(1 << 30)
+
+#define DDR_MRS_CAS(n)		(n << 4)
+#define DDR_MRS_WR(n)		((n-1) << 9)
+#define MICRON_INIT_DEV_OP	0x01000002 | DDR_MRS_WR(2) | DDR_MRS_CAS(3)
+#define ELPIDA_INIT_DEV_OP	0x01000002 | DDR_MRS_WR(4) | DDR_MRS_CAS(4)
+#define DDR_NOP			0x01380000
+#define DDR_PCHG_ALL		0x01100400
+#define DDR_EM2			0x01020000
+#define DDR_EM3			0x01030000
+#define DDR_EN_DLL		0x01010000
+#define DDR_RES_DLL		0x01000932
+#define DDR_RFSH		0x01080000
+#define DDR_OCD_DEFAULT		0x01010780
+#define DDR_OCD_EXIT		0x01010400
 
 /* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+#define MDDRCGRP_PM_CFG1	0x00077777
+#define MDDRCGRP_PM_CFG2	0x00000000
+#define MDDRCGRP_HIPRIO_CFG	0x00000001
+#define MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define MDDRCGRP_LUT1_MU	0x66666666
+#define MDDRCGRP_LUT1_ML	0x55555555
+#define MDDRCGRP_LUT2_MU	0x44444444
+#define MDDRCGRP_LUT2_ML	0x44444444
+#define MDDRCGRP_LUT3_MU	0x55555555
+#define MDDRCGRP_LUT3_ML	0x55555558
+#define MDDRCGRP_LUT4_MU	0x11111111
+#define MDDRCGRP_LUT4_ML	0x11111122
+#define MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define MDDRCGRP_LUT1_AU	0x66666666
+#define MDDRCGRP_LUT1_AL	0x66666666
+#define MDDRCGRP_LUT2_AU	0x11111111
+#define MDDRCGRP_LUT2_AL	0x11111111
+#define MDDRCGRP_LUT3_AU	0x11111111
+#define MDDRCGRP_LUT3_AL	0x11111111
+#define MDDRCGRP_LUT4_AU	0x11111111
+#define MDDRCGRP_LUT4_AL	0x11111111
 
 /*
  * NOR FLASH on the Local Bus
@@ -200,6 +216,42 @@
 #undef CONFIG_SYS_FLASH_CHECKSUM
 
 /*
+ * NAND FLASH
+ * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon/rev 4 boards only)
+ */
+#define CONFIG_NAND_FSL_NFC
+#ifdef CONFIG_NAND_FSL_NFC
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#endif
+#define CONFIG_CMD_NAND 1
+/*
+ * The flash on ADS5121 board is two flash chips in one package
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define NAND_MAX_CHIPS		CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE	1
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH 1
+#define CONFIG_FSL_NFC_WRITE_SIZE 2048
+#define CONFIG_FSL_NFC_SPARE_SIZE 64
+#define CONFIG_FSL_NFC_CHIPS 2
+
+#ifndef __ASSEMBLY__
+/*
+ * ADS board as a custom chip select
+ */
+extern void ads5121_fsl_nfc_board_cs(int);
+#define CONFIG_FSL_NFC_BOARD_CS_FUNC ads5121_fsl_nfc_board_cs
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_NAND_FSL_NFC */
+
+
+/*
  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
  * window is 64KB
  */
@@ -222,7 +274,7 @@
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)		/* Reserve 512 kB for Mon */
 #ifdef	CONFIG_FSL_DIU_FB
 #define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
 #else
@@ -238,6 +290,7 @@
 /*
  * Serial console configuration
  */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
 #define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
 #if CONFIG_PSC_CONSOLE != 3
 #error CONFIG_PSC_CONSOLE must be 3
@@ -318,12 +371,6 @@
 #define CONFIG_HAS_ETH0
 
 /*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
-
-/*
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -349,12 +396,13 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
+#undef CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-#undef CONFIG_CMD_FUSE
+#undef CONFIG_CMD_DATE
+#define CONFIG_IMM		/* needed for CONFIG_CMD_FUSE */
+#define CONFIG_CMD_FUSE
 #define CONFIG_CMD_IDE
 #define CONFIG_CMD_EXT2
 
@@ -410,8 +458,8 @@
 #define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
 #endif
 
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT	HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK | HID0_ICE
 #define CONFIG_SYS_HID2	HID2_HBE
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
@@ -462,12 +510,14 @@
 	"u-boot=ads5121/u-boot.bin\0"					\
 	"bootfile=ads5121/uImage\0"					\
 	"fdtfile=ads5121/ads5121.dtb\0"					\
-	"rootpath=/opt/eldk/ppc_6xx\n"					\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
 	"netdev=eth0\0"							\
 	"consdev=ttyPSC0\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+		"nfsroot=${serverip}:${rootpath} ${othbootargs}\0"	\
+	"ramargs=setenv bootargs root=/dev/ram rw ${othbootargs}\0"	\
+	"jffs2args=setenv bootargs root=/dev/mtdblock1 rw "		\
+		"rootfstype=jffs2 ${othbootargs}\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
@@ -486,6 +536,8 @@
 		"tftp ${fdt_addr_r} ${fdtfile};"			\
 		"run ramargs addip addtty;"				\
 		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"flash_jffs2=run jffs2args addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
 	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
 	"update=protect off ${u-boot_addr} +${filesize};"		\
 		"era ${u-boot_addr} +${filesize};"			\
@@ -493,7 +545,7 @@
 	"upd=run load update\0"						\
 	""
 
-#define CONFIG_BOOTCOMMAND	"run flash_self"
+#define CONFIG_BOOTCOMMAND	"run flash_jffs2"
 
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
diff --git a/include/configs/ads5125.h b/include/configs/ads5125.h
new file mode 100644
index 00000000000..1393665802c
--- /dev/null
+++ b/include/configs/ads5125.h
@@ -0,0 +1,650 @@
+/*
+ * (C) Copyright 2008-2009 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * ADS5125 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ADS5125
+/*
+ * Memory map for the ADS5125 board:
+ *
+ * 0x0000_0000 - 0x00FF_FFFF	DDR RAM (16 MB)
+ * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
+ * 0x4000_0000 - 0x400F_FFFF	NAND FLASH CONTROLLER
+ * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
+ * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC512X		1	/* MPC512X family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_NAND
+#endif
+
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_YAFFS2
+#define	CONFIG_UBOOT_YAFFS2_START	0xc00000
+#define	CONFIG_UBOOT_YAFFS2_SIZE		0x10c00000
+#define	BOARD_TYPE_ADS5125	1
+#define	BOARD_TYPE_5125_MPU	2
+#define	BOARD_TYPE			BOARD_TYPE_5125_MPU
+
+#define	HDMI_CHIP_SIL9034	1
+#define	HDMI_CHIP_SIL9022A	2
+#define	HDMI_CHIP_SELECT	HDMI_CHIP_SIL9022A
+#if (HDMI_CHIP_SELECT==HDMI_CHIP_SIL9022A)
+#define CONFIG_HDMI_CHIP_SIL9022A
+#endif
+#define CONFIG_MISC_INIT_R
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+/*
+ * Enable Fast boot
+ */
+#define CONFIG_FASTBOOT
+
+#define CONFIG_SYS_MPC512X_CLKIN	32768000 	/* in Hz Change by Cloudy Chen<chen_yunsong@mtcera.com> */
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+/*
+#define CONFIG_MISC_INIT_R
+*/
+
+#define CFG_SYS_IMMR		0x80000000
+#define CFG_IMMR		0x80000000
+#define CONFIG_SYS_IMMR		0x80000000
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
+#define CONFIG_SYS_IOCTRL_ADDR		(CONFIG_SYS_IMMR+0xA000)
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+
+#define CFG_DDR_BASE		CONFIG_SYS_DDR_BASE
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+
+#define MDDRC_SYS_CFG		0xfa804A00
+#define MDDRC_SYS_CFG_RUN	0xea804A00
+#define CFG_MDDRC_SYS_CFG_RUN	MDDRC_SYS_CFG_RUN
+
+#define MDDRC_TIME_CFG1		0x68ec1189	//0x690e1189
+#define CFG_MDDRC_TIME_CFG1	MDDRC_TIME_CFG1
+#define MDDRC_TIME_CFG2		0x34310864	//0x34a90864
+#define CFG_MDDRC_TIME_CFG2	MDDRC_TIME_CFG2
+#define MDDRC_SYS_CFG_EN	0xF0000000
+#define CFG_MDDRC_SYS_CFG_EN	MDDRC_SYS_CFG_EN
+#define MDDRC_TIME_CFG0		0x00003c2d	//0x00003D2E
+#define CFG_MDDRC_TIME_CFG0	MDDRC_TIME_CFG0
+#define MDDRC_TIME_CFG0_RUN	0x06183c2d
+#define CFG_MDDRC_TIME_CFG0_RUN		MDDRC_TIME_CFG0_RUN
+
+#define DDR_ODT_150		0x40
+#define DDR_ODT_75		0x04
+#define DDR_ODT_50		0x44
+#define DDR_OCD_DFLT_MASK	0x00000380
+#define DDR_MRS_CAS(n)		(n << 4)
+#define DDR_MRS_WR(n)		((n-1) << 9)
+#define MDDRC_SYS_CFG_CLK_BIT       (1 << 29)
+#define MDDRC_SYS_CFG_CKE_BIT       (1 << 30)
+
+#define DDR_RFSH		0x01080000
+#define CFG_MICRON_RFSH	DDR_RFSH
+#define DDR_INIT_DEV_OP		0x01000432 /*0x01000002 | DDR_MRS_WR(4) | DDR_MRS_CAS(4)*/
+#define CFG_MICRON_INIT_DEV_OP	DDR_INIT_DEV_OP
+#define DDR_NOP			0x01380000
+#define CFG_MICRON_NOP		DDR_NOP
+#define DDR_PCHG_ALL		0x01100400
+#define CFG_MICRON_PCHG_ALL	DDR_PCHG_ALL
+#define DDR_EM2			0x01020000
+#define CFG_MICRON_EM2		DDR_EM2
+#define DDR_EM3			0x01030000
+#define CFG_MICRON_EM3		DDR_EM3
+#define DDR_EN_DLL		0x01010000
+#define CFG_MICRON_EN_DLL	DDR_EN_DLL
+#define DDR_RES_DLL		DDR_INIT_DEV_OP | 0x00000100
+#define DDR_RFSH		0x01080000
+#define DDR_OCD_DEFAULT		0x01010400 | DDR_OCD_DFLT_MASK | DDR_ODT_50
+#define CFG_MICRON_OCD_DEFAULT	DDR_OCD_DEFAULT
+#define DDR_OCD_EXIT		DDR_OCD_DEFAULT & ~DDR_OCD_DFLT_MASK
+
+/* DDR Priority Manager Configuration */
+#define MDDRCGRP_PM_CFG1	0x000777aa	//0x00077777
+#define CFG_MDDRCGRP_PM_CFG1 	MDDRCGRP_PM_CFG1
+#define MDDRCGRP_PM_CFG2	0x00000055	//0x00000000
+#define CFG_MDDRCGRP_PM_CFG2 	MDDRCGRP_PM_CFG2
+#define MDDRCGRP_HIPRIO_CFG	0x00000000	//0x00000001
+#define CFG_MDDRCGRP_HIPRIO_CFG	MDDRCGRP_HIPRIO_CFG
+#define MDDRCGRP_LUT0_MU	0x11111117	//0xFFEEDDCC
+#define CFG_MDDRCGRP_LUT0_MU	MDDRCGRP_LUT0_MU
+#define MDDRCGRP_LUT0_ML	0x7777777a	//0xBBAAAAAA
+#define CFG_MDDRCGRP_LUT0_ML	MDDRCGRP_LUT0_ML
+#define MDDRCGRP_LUT1_MU	0x444eeeee	//0x66666666
+#define CFG_MDDRCGRP_LUT1_MU	MDDRCGRP_LUT1_MU
+#define MDDRCGRP_LUT1_ML	0xeeeeeeee	//0x55555555
+#define CFG_MDDRCGRP_LUT1_ML	MDDRCGRP_LUT1_ML
+#define MDDRCGRP_LUT2_MU	0x44444444
+#define CFG_MDDRCGRP_LUT2_MU	MDDRCGRP_LUT2_MU
+#define MDDRCGRP_LUT2_ML	0x44444444
+#define CFG_MDDRCGRP_LUT2_ML	MDDRCGRP_LUT2_ML
+#define MDDRCGRP_LUT3_MU	0x55555555
+#define CFG_MDDRCGRP_LUT3_MU	MDDRCGRP_LUT3_MU
+#define MDDRCGRP_LUT3_ML	0x55555558
+#define CFG_MDDRCGRP_LUT3_ML	MDDRCGRP_LUT3_ML
+#define MDDRCGRP_LUT4_MU	0x11111111
+#define CFG_MDDRCGRP_LUT4_MU	MDDRCGRP_LUT4_MU
+#define MDDRCGRP_LUT4_ML	0x1111117c	//0x11111122
+#define CFG_MDDRCGRP_LUT4_ML	MDDRCGRP_LUT4_ML
+#define MDDRCGRP_LUT0_AU	0x33333377	//0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT0_AU	MDDRCGRP_LUT0_AU
+#define MDDRCGRP_LUT0_AL	0x7777eeee //0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT0_AL	MDDRCGRP_LUT0_AL
+#define MDDRCGRP_LUT1_AU		0x11111111	//0x66666666
+#define CFG_MDDRCGRP_LUT1_AU 	MDDRCGRP_LUT1_AU
+#define MDDRCGRP_LUT1_AL	0x11111111	//0x66666666
+#define CFG_MDDRCGRP_LUT1_AL	MDDRCGRP_LUT1_AL
+#define MDDRCGRP_LUT2_AU	0x11111111
+#define CFG_MDDRCGRP_LUT2_AU 	MDDRCGRP_LUT2_AU
+#define MDDRCGRP_LUT2_AL	0x11111111
+#define CFG_MDDRCGRP_LUT2_AL	MDDRCGRP_LUT2_AL
+#define MDDRCGRP_LUT3_AU	0x11111111
+#define CFG_MDDRCGRP_LUT3_AU	MDDRCGRP_LUT3_AU
+#define MDDRCGRP_LUT3_AL	0x11111111
+#define CFG_MDDRCGRP_LUT3_AL	MDDRCGRP_LUT3_AL
+#define MDDRCGRP_LUT4_AU	0x11111111
+#define CFG_MDDRCGRP_LUT4_AU	MDDRCGRP_LUT4_AU
+#define MDDRCGRP_LUT4_AL	0x11111111
+#define CFG_MDDRCGRP_LUT4_AL	MDDRCGRP_LUT4_AL
+
+#define IOCTRL_MUX_CS2	0x43	/* CS2 IO pin must be set in start.S */
+#define IOCTRL_MUX_PSC9	0x23	/* ditto for UART1 in case it's Console  */
+#define IOCTRL_GBOBE_ON	0x01
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+ #if(BOARD_TYPE==BOARD_TYPE_5125_MPU)
+#define CONFIG_SYS_NO_FLASH
+ #define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
+ #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+ #else
+#undef CONFIG_BKUP_FLASH
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#ifdef CONFIG_BKUP_FLASH
+/* Backup and main flash may not be the same size & same sector in the future */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		0x02000000	/* max flash size in bytes */
+#else
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		0x02000000	/* max flash size in bytes */
+#endif
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CFG_FLASH_SIZE	CONFIG_SYS_FLASH_SIZE
+#endif
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * NAND FLASH
+ * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon/rev 4 boards only)
+ */
+#define RCWHR		0xe04
+#define NAND_BOOT	(1<<5)
+/*
+#define CONFIG_NAND_SPL
+*/
+#define CONFIG_NAND_FSL_NFC
+#ifdef CONFIG_NAND_FSL_NFC
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#define CONFIG_SYS_NAND_SPACE		0x100000
+#define CFG_FLASH_BASE		CONFIG_SYS_NAND_BASE
+#define	CFG_FLASH_SIZE		CONFIG_SYS_NAND_SPACE
+#define CFG_NAND_U_BOOT_SIZE  (256 << 10)
+#define	CFG_LOADER_DDR_START		0x00100000
+#define CFG_NAND_U_BOOT_DST   (0x1000000)
+#define CFG_NAND_U_BOOT_START (CFG_NAND_U_BOOT_DST+0x100) /* 1st 2K page of NAND is copied so *
+					  * we need to offset by 0x800       */
+
+#else
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#endif
+#define CONFIG_CMD_NAND 1
+
+#define CFG_NAND_BASE CONFIG_SYS_NAND_BASE
+/*
+ * The flash on ADS5121 board is two flash chips in one package
+ */
+ #define CFG_NAND_BLOCK_SIZE	0x20000	/* 128K, 64 x 2K opages per block */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE	1
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+ 
+
+#define CONFIG_FSL_NFC_WRITE_SIZE 4096
+#define CONFIG_FSL_NFC_SPARE_SIZE 128
+
+#define CONFIG_FSL_NFC_WIDTH 1
+
+#define CONFIG_FSL_NFC_CHIPS 1
+
+#ifndef __ASSEMBLY__
+/*
+ * ADS board as a custom chip select
+ */
+extern void ads5125_fsl_nfc_board_cs(int);
+#define CONFIG_FSL_NFC_BOARD_CS_FUNC ads5125_fsl_nfc_board_cs
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_NAND_FSL_NFC */
+
+#if(BOARD_TYPE!=BOARD_TYPE_5125_MPU)
+/*
+ * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
+ * window is 64KB
+ */
+#define CONFIG_SYS_CPLD_BASE		0x82000000
+#define CONFIG_SYS_CPLD_SIZE		0x00010000	/* 64 KB */
+#define IS_CFG1_SWITCH		(in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x13)) & 0x80)
+#endif
+
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00008000	/* 32 KB */
+#define CFG_SRAM_BASE		CONFIG_SYS_SRAM_BASE
+#define CFG_SRAM_SIZE		CONFIG_SYS_SRAM_SIZE	/* 32 KB */
+
+
+#define CONFIG_SYS_CS0_CFG		0x05059110	/* ALE active low, data size 2bytes */
+#define CONFIG_SYS_CS2_CFG		0x05059010	/* ALE active low, data size 1byte  */
+#define CONFIG_SYS_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_SRAM_SIZE		/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
+#define CFG_MONITOR_BASE	CONFIG_SYS_MONITOR_BASE		/* Start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)		/* Reserve 256 kB for Mon */
+/* Use SRAM for initial stack */
+#define CFG_INIT_RAM_ADDR	CFG_SRAM_BASE		/* Initial RAM address */
+#define CFG_INIT_RAM_END	CFG_SRAM_SIZE		/* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	CONFIG_SYS_GBL_DATA_SIZE			/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET	CONFIG_SYS_INIT_SP_OFFSET
+
+#ifdef	CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_SPLASH_SIZE		(2 * 1024 * 1024)
+#else
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC9 */
+#if CONFIG_PSC_CONSOLE != 1
+#error CONFIG_PSC_CONSOLE must be 1
+#endif
+#define CONFIG_PSC_CONSOLE2	9	/* other console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC1_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC1_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC1_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC1_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* defd in ads5121 I2C with hardware support */
+#undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#if 0
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#endif
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5	/* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+
+#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC	1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR		0x1
+#define CONFIG_PHY2_ADDR	0x1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_FEC_AN_TIMEOUT	1
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+
+/*
+ * Environment
+ */
+ #if defined(CONFIG_NAND_U_BOOT)
+#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-0x2000)
+#define CONFIG_SYS_ENV_ADDR	CONFIG_ENV_ADDR
+#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_OFFSET		(512 * 1024)
+#define CONFIG_ENV_SECT_SIZE	CFG_NAND_BLOCK_SIZE
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_SYS_ENV_SIZE	CONFIG_ENV_SIZE
+
+#define CMD_SAVEENV
+#define	CONFIG_ENV_START_PAGE		0x200
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#elif !defined(CFG_RAMBOOT)
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the Flash sector size */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_ENV_SIZE		0x2000
+#define CONFIG_ENV_SIZE		0x2000
+#ifdef CONFIG_BKUP_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (128K) for env */
+#define CONFIG_SYS_ENV_SECT_SIZE	0x20000	/* one sector (128K) for env */
+#else
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (128K) for env */
+#define CONFIG_SYS_ENV_SECT_SIZE	0x20000	/* one sector (128K) for env */
+#endif
+#else
+#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_ENV_ADDR + CONFIG_SYS_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#endif
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5125e Reference Manual.
+ */
+/* #define CONFIG_WATCHDOG */		/* enable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CONFIG_SYS_HID0_INIT   HID0_ICE | HID0_ICFI
+#define CFG_HID0_INIT CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID0_FINAL  HID0_ENABLE_MACHINE_CHECK | HID0_ICE
+#define CONFIG_SYS_HID2	HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME		ads5125
+#define CONFIG_BOOTFILE		ads5125/uImage
+#define CONFIG_ROOTPATH		/opt/eldk/pcc_6xx
+
+#define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	2	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\	
+	"ethaddr=AA:BB:CC:DD:EE:FF\0"				\
+	"ramdiskfile=ads5125/uRamdisk\0"				\
+	"fdtfile=ads5125/ads5125.dtb\0"					\
+	"u-boot=ads5125/u-boot.bin\0"					\
+	"netdev=eth0\0"							\
+	"ipaddr=192.168.10.205\0"						\
+	"consdev=tty0\0"						\
+	"serverip=192.168.10.74\0"						\
+	"fdtaddr=4000000\0"						\
+	"fdtfile=mpc5125-twr.dtb\0"						\
+	"kernel_name=vmlinux-twr-5125.bin\0"						\
+	"consoledev=ttyPSC0\0"						\
+	"flash_kernel=0x300\0"						\
+	"flash_dtb=0xb00\0"						\
+	"nandboot=setenv bootargs root=/dev/mtdblock6 rw rootfstype=yaffs2 console=$consdev,$baudrate;"\
+	"nand_r $kernel_loader_addr $flash_kernel 0x400000;nand_r $fdt_loader_addr $flash_dtb 0x3000;bootm $kernel_loader_addr - $fdt_loader_addr\0" \	
+	"fdt_name=mpc5125-twr.dtb\0"						\
+	"ramdisk_name=rootfs.ext2.gz.uboot-common\0"						\
+	"ramdisk_flash_addr=0xc00\0"							\
+	"kernel_loader_addr=0x2000000\0"						\
+	"fdt_loader_addr=0x2800000\0"							\
+	"ramdisk_loader_addr=0x3000000\0"						\
+	"nand_ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate;"\
+	"nand_r 0x2000000 $flash_kernel 0x400000;nand_r 0x2800000 $flash_dtb 0x3000;nand_r 0x3000000 0xc00  0x500000;;bootm $kernel_loader_addr $ramdisk_loader_addr $fdt_loader_addr\0"							\
+	"uboot_name=u-boot-second-usb.bin\0"						\
+	"uboot_name_first=u-boot-first-usb.bin\0"						\
+	"uboot_size=0x60000\0"						\
+	"uboot_update=tftp 0x1000000 u-boot-spl-2k.bin;nand_e 0x00 0x01;nand_loader 0x1000000 0x00 0x800;"\
+	"tftp 0x1000000 $uboot_name_first ;nand_w 0x1000000 0x8 0x60000;"		\
+	"tftp 0x1000000 $uboot_name ;nand_e 0x100 0x101;nand_w 0x1000000 0x100 0x60000\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\	
+	"mqx_name=extram_d.bin\0"						\
+	"mqx_size=0xa00000\0"							\
+	"mqx_addr=0x10000\0"						\
+	"mqx_flash_addr_s=0x80000\0"						\
+	"mqx_flash_addr_e=0x863ff\0"						\
+	"kernel_rootfs_update=tftp 0x3000000  $fdt_name;nand_e $flash_dtb 0xb01;nand_w 0x3000000 $flash_dtb 0x3000;tftp 0x3000000 $kernel_name;nand_e $flash_kernel 0xaff;nand_w 0x3000000 $flash_kernel 0x400000;tftp 0x3000000 $ramdisk_name;nand_e 0xc00 0x13ff;nand_w 0x3000000 0xc00 0x500000\0"						\
+	"mqx_update=tftp $mqx_addr $mqx_name;nand_e $mqx_flash_addr_s $mqx_flash_addr_e;nand_w $mqx_addr $mqx_flash_addr_s $mqx_size\0"\
+	"mqxboot=nand_r $mqx_addr $mqx_flash_addr_s $mqx_size;go $mqx_addr\0"		\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run nandboot"
+
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
+
+#define OF_CPU			"PowerPC,5125@0"
+#define OF_SOC_COMPAT		"fsl,mpc5125-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
+
+#endif	/* __CONFIG_H */
diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h
index 9036b74f86e..32b1900b1e4 100644
--- a/include/linux/mtd/compat.h
+++ b/include/linux/mtd/compat.h
@@ -24,7 +24,7 @@
 #define vfree(ptr)				free(ptr)
 
 #define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
-
+#define LINUX_VERSION_CODE KERNEL_VERSION(2,6,29)
 /*
  * ..and if you can't take the strict
  * types, you can specify one yourself.
diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index 410c5dd2fb4..8d5f60c75ea 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -123,7 +123,7 @@ struct nand_oobfree {
  */
 struct nand_ecclayout {
 	uint32_t eccbytes;
-	uint32_t eccpos[64];
+	uint32_t eccpos[128];
 	uint32_t oobavail;
 	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
 };
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 354e3a0bc47..e9bf5c4a8a8 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -110,7 +110,7 @@ struct mtd_oob_ops {
 struct mtd_info {
 	u_char type;
 	u_int32_t flags;
-	u_int32_t size;	 /* Total size of the MTD */
+	u_int64_t size;	 /* Total size of the MTD */
 
 	/* "Major" erase size for the device. Naïve users may take this
 	 * to be the only erase size available, or may use the more detailed
@@ -268,11 +268,13 @@ int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs,
 #ifdef CONFIG_MTD_PARTITIONS
 void mtd_erase_callback(struct erase_info *instr);
 #else
+/*
 static inline void mtd_erase_callback(struct erase_info *instr)
 {
 	if (instr->callback)
 		instr->callback(instr);
 }
+*/
 #endif
 
 /*
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index a4ad5711d6c..212a593b971 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -396,7 +396,7 @@ struct nand_chip {
 	int		bbt_erase_shift;
 	int		chip_shift;
 	int		numchips;
-	unsigned long	chipsize;
+	u64		chipsize;
 	int		pagemask;
 	int		pagebuf;
 	int		subpagesize;
@@ -454,7 +454,7 @@ struct nand_flash_dev {
 	char *name;
 	int id;
 	unsigned long pagesize;
-	unsigned long chipsize;
+	u64 chipsize;
 	unsigned long erasesize;
 	unsigned long options;
 };
diff --git a/include/mpc5125_nfc.h b/include/mpc5125_nfc.h
new file mode 100644
index 00000000000..cd3e6c61c4a
--- /dev/null
+++ b/include/mpc5125_nfc.h
@@ -0,0 +1,357 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Shaohui Xie <b21989@freescale.com>
+ *
+ * Description:
+ * MPC5125 Nand driver.
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef MPC5125_NFC_H
+#define MPC5125_NFC_H
+
+/* I/O Control Register OFFSETS */
+#define NFC_CE0			1
+#define NFC_CE1			2
+#define NFC_CE2			4
+#define NFC_CE3			8
+#define NFC_SEL_RB0			1
+#define NFC_SEL_RB1			2
+#define NFC_SEL_RB2			4
+#define NFC_SEL_RB3			8
+
+/******************** IO control fields ************************/
+#define DS_MSR_1			0x00
+#define DS_MSR_2			0x01
+#define DS_MSR_3			0x02
+#define DS_MSR_4			0x03
+#define ST_Disabled			0x00
+#define ST_Enabled			0x04
+#define PAD_FUNC0			0x00
+#define PAD_FUNC1			0x20
+#define PAD_FUNC2			0x40
+#define PAD_FUNC3			0x60
+#define PUD_PUE			0x18
+/**************************************************************/
+
+/* Chip select and rb select Define */
+
+/* NFC PAD Define */
+#define PAD_NFC_IO                	PAD_FUNC0
+#define PAD_NFC_ALE               	PAD_FUNC0
+#define PAD_NFC_CLE               	PAD_FUNC0
+#define PAD_NFC_WE                	PAD_FUNC0
+#define PAD_NFC_RE                	PAD_FUNC0
+#define PAD_NFC_CE0               	PAD_FUNC0
+#define PAD_NFC_CE1               	PAD_FUNC1
+#define PAD_NFC_CE2               	PAD_FUNC2
+#define PAD_NFC_CE3               	PAD_FUNC2
+#define PAD_NFC_RB0               	PAD_FUNC0
+#define PAD_NFC_RB1               	PAD_FUNC2
+#define PAD_NFC_RB2               	PAD_FUNC2
+#define PAD_NFC_RB3               	PAD_FUNC2
+
+/* NFC Control PAD Define */
+#define BALL_NFC_CE0			IOCTL_NFC_CE0_B
+#define BALL_NFC_CE1			IOCTL_SDHC1_CLK
+#define BALL_NFC_CE2			IOCTL_PSC1_4
+#define BALL_NFC_CE3			IOCTL_J1850_TX
+#define BALL_NFC_RB0			IOCTL_NFC_RB
+#define BALL_NFC_RB1			IOCTL_FEC1_TXD_0
+#define BALL_NFC_RB2			IOCTL_PSC1_3
+#define BALL_NFC_RB3			IOCTL_J1850_RX
+#define BALL_NFC_ALE			IOCTL_EMB_AD19
+#define BALL_NFC_CLE			IOCTL_EMB_AD18
+#define BALL_NFC_WE			IOCTL_EMB_AD16
+#define BALL_NFC_RE			IOCTL_EMB_AD17
+
+/* NFC IO Pad Define */
+#define BALL_NFC_IO0			IOCTL_EMB_AD00
+#define BALL_NFC_IO1			IOCTL_EMB_AD01
+#define BALL_NFC_IO2			IOCTL_EMB_AD02
+#define BALL_NFC_IO3			IOCTL_EMB_AD03
+#define BALL_NFC_IO4			IOCTL_EMB_AD04
+#define BALL_NFC_IO5			IOCTL_EMB_AD05
+#define BALL_NFC_IO6			IOCTL_EMB_AD06
+#define BALL_NFC_IO7			IOCTL_EMB_AD07
+
+/* Addresses for NFC MAIN RAM BUFFER areas */
+#define NFC_MAIN_AREA(n)	((n) *  0x1000)
+
+/* Addresses for NFC SPARE BUFFER areas */
+#define NFC_SPARE_BUFFERS		8
+#define NFC_SPARE_LEN			0x10
+#define NFC_SPARE_AREA(n)		(0x800 + NFC_MAIN_AREA(n) )
+
+#define PAGE_2K                   	0x0800
+#define PAGE_64                   	0x0040
+
+/* MPC5125 NFC registers */
+/* Typical Flash Commands */
+#define READ_PAGE_CMD_CODE		0x7EE0
+#define PROGRAM_PAGE_CMD_CODE		0x7FC0
+#define ERASE_CMD_CODE			0x4EC0
+#define READ_ID_CMD_CODE		0x4804
+#define RESET_CMD_CODE			0x4040
+#define DMA_PROGRAM_PAGE_CMD_CODE	0xFFC8
+#define RANDOM_IN_CMD_CODE		0x7140
+#define RANDOM_OUT_CMD_CODE		0x70E0
+#define STATUS_READ_CMD_CODE		0x4068
+
+#define PAGE_READ_CMD_BYTE1		0x00
+#define PAGE_READ_CMD_BYTE2		0x30
+#define PROGRAM_PAGE_CMD_BYTE1		0x80
+#define PROGRAM_PAGE_CMD_BYTE2		0x10
+#define READ_STATUS_CMD_BYTE		0x70
+#define ERASE_CMD_BYTE1		0x60
+#define ERASE_CMD_BYTE2		0xD0
+#define READ_ID_CMD_BYTE		0x90
+#define RESET_CMD_BYTE			0xFF
+#define RANDOM_OUT_CMD_BYTE1		0x05
+#define RANDOM_OUT_CMD_BYTE2		0xE0
+
+/* NFC ECC mode define */
+#define ECC_BYPASS			0x0
+#define ECC_8_BYTE			0x1
+#define ECC_12_BYTE			0x2
+#define ECC_15_BYTE			0x3
+#define ECC_23_BYTE			0x4
+#define ECC_30_BYTE			0x5
+#define ECC_45_BYTE			0x6
+#define ECC_60_BYTE			0x7
+#define ECC_ERROR			1
+#define ECC_RIGHT			0
+
+/***************** Module-Relative Register Offsets *************************/
+#define NFC_SRAM_BUFFER                0x0000
+#define NFC_FLASH_CMD1 		0x3F00
+#define NFC_FLASH_CMD2			0x3F04
+#define NFC_COL_ADDR			0x3F08
+#define NFC_ROW_ADDR			0x3F0c
+#define NFC_FLASH_COMMAND_REPEAT	0x3F10
+#define NFC_ROW_ADDR_INC		0x3F14
+#define NFC_FLASH_STATUS1		0x3F18
+#define NFC_FLASH_STATUS2		0x3F1c
+#define NFC_DMA1_ADDR			0x3F20
+#define NFC_DMA2_ADDR			0x3F34
+#define NFC_DMA_CONFIG			0x3F24
+#define NFC_CACHE_SWAP			0x3F28
+#define NFC_SECTOR_SIZE		0x3F2c
+#define NFC_FLASH_CONFIG		0x3F30
+#define NFC_IRQ_STATUS			0x3F38
+
+/***************** Module-Relative Register Reset Value *********************/
+#define NFC_SRAM_BUFFER_RSTVAL                	0x00000000
+#define NFC_FLASH_CMD1_RSTVAL 			0x30FF0000
+#define NFC_FLASH_CMD2_RSTVAL			0x007EE000
+#define NFC_COL_ADDR_RSTVAL			0x00000000
+#define NFC_ROW_ADDR_RSTVAL			0x11000000
+#define NFC_FLASH_COMMAND_REPEAT_RSTVAL	0x00000000
+#define NFC_ROW_ADDR_INC_RSTVAL		0x00000001
+#define NFC_FLASH_STATUS1_RSTVAL		0x00000000
+#define NFC_FLASH_STATUS2_RSTVAL		0x00000000
+#define NFC_DMA1_ADDR_RSTVAL			0x00000000
+#define NFC_DMA2_ADDR_RSTVAL			0x00000000
+#define NFC_DMA_CONFIG_RSTVAL			0x00000000
+#define NFC_CACHE_SWAP_RSTVAL			0x0FFE0FFE
+#define NFC_SECTOR_SIZE_RSTVAL			0x00000420
+#define NFC_FLASH_CONFIG_RSTVAL		0x000EA631
+#define NFC_IRQ_STATUS_RSTVAL			0x04000000
+
+/***************** Module-Relative Register Mask *************************/
+
+/* NFC_FLASH_CMD1 Field */
+#define CMD1_MASK				0xFFFF0000
+#define CMD1_SHIFT				0
+#define CMD_BYTE2_MASK    			0xFF000000
+#define CMD_BYTE2_SHIFT   			24
+#define CMD_BYTE3_MASK    			0x00FF0000
+#define CMD_BYTE3_SHIFT   			16
+
+/* NFC_FLASH_CM2 Field */
+#define CMD2_MASK				0xFFFFFF07
+#define CMD2_SHIFT				0
+#define CMD_BYTE1_MASK			    	0xFF000000
+#define CMD_BYTE1_SHIFT   			24
+#define CMD_CODE_MASK				0x00FFFF00
+#define CMD_CODE_SHIFT				8
+#define BUFNO_MASK				0x00000006
+#define BUFNO_SHIFT				1
+#define BUSY_MASK				0x00000001
+#define BUSY_SHIFT				0
+#define START_MASK				0x00000001
+#define START_SHIFT				0
+
+/* NFC_COL_ADDR Field */
+#define COL_ADDR_MASK				0x0000FFFF
+#define COL_ADDR_SHIFT				0
+#define COL_ADDR_COL_ADDR2_MASK		0x0000FF00
+#define COL_ADDR_COL_ADDR2_SHIFT		8
+#define COL_ADDR_COL_ADDR1_MASK		0x000000FF
+#define COL_ADDR_COL_ADDR1_SHIFT		0
+
+/* NFC_ROW_ADDR Field */
+#define ROW_ADDR_MASK				0x00FFFFFF
+#define ROW_ADDR_SHIFT				0
+#define ROW_ADDR_CHIP_SEL_RB_MASK		0xF0000000
+#define ROW_ADDR_CHIP_SEL_RB_SHIFT		28
+#define ROW_ADDR_CHIP_SEL_MASK			0x0F000000
+#define ROW_ADDR_CHIP_SEL_SHIFT		24
+#define ROW_ADDR_ROW_ADDR3_MASK		0x00FF0000
+#define ROW_ADDR_ROW_ADDR3_SHIFT		16
+#define ROW_ADDR_ROW_ADDR2_MASK		0x0000FF00
+#define ROW_ADDR_ROW_ADDR2_SHIFT		8
+#define ROW_ADDR_ROW_ADDR1_MASK		0x000000FF
+#define ROW_ADDR_ROW_ADDR1_SHIFT		0
+
+/* NFC_FLASH_COMMAND_REPEAT Field */
+#define COMMAND_REPEAT_MASK			0x0000FFFF
+#define COMMAND_REPEAT_SHIFT			0
+#define COMMAND_REPEAT_REPEAT_COUNT_MASK	0x0000FFFF
+#define COMMAND_REPEAT_REPEAT_COUNT_SHIFT	0
+
+/* NFC_ROW_ADDR_INC Field */
+#define ROW_ADDR_INC_MASK			0x00FFFFFF
+#define ROW_ADDR_INC_SHIFT			0
+#define ROW_ADDR_INC_ROW_ADDR3_INC_MASK	0x00FF0000
+#define ROW_ADDR_INC_ROW_ADDR3_INC_SHIFT	16
+#define ROW_ADDR_INC_ROW_ADDR2_INC_MASK	0x0000FF00
+#define ROW_ADDR_INC_ROW_ADDR2_INC_SHIFT	8
+#define ROW_ADDR_INC_ROW_ADDR1_INC_MASK	0x000000FF
+#define ROW_ADDR_INC_ROW_ADDR1_INC_SHIFT	0
+
+/* NFC_FLASH_STATUS1 Field */
+#define STATUS1_MASK				0xFFFFFFFF
+#define STATUS1_SHIFT				0
+#define STATUS1_ID_BYTE1_MASK			0xFF000000
+#define STATUS1_ID_BYTE1_SHIFT			24
+#define STATUS1_ID_BYTE2_MASK			0x00FF0000
+#define STATUS1_ID_BYTE2_SHIFT			16
+#define STATUS1_ID_BYTE3_MASK			0x0000FF00
+#define STATUS1_ID_BYTE3_SHIFT			8
+#define STATUS1_ID_BYTE4_MASK			0x000000FF
+#define STATUS1_ID_BYTE4_SHIFT			0
+
+/* NFC_FLASH_STATUS2 Field */
+#define STATUS2_MASK				0xFF0000FF
+#define STATUS2_SHIFT				0
+#define STATUS2_ID_BYTE5_MASK			0xFF000000
+#define STATUS2_ID_BYTE5_SHIFT			24
+#define STATUS_BYTE1_MASK			0x000000FF
+#define STATUS2_STATUS_BYTE1_SHIFT		0
+
+/* NFC_DMA1_ADDR Field */
+#define DMA1_ADDR_MASK				0xFFFFFFFF
+#define DMA1_ADDR_SHIFT			0
+#define DMA1_ADDR_DMA1_ADDR_MASK		0xFFFFFFFF
+#define DMA1_ADDR_DMA1_ADDR_SHIFT		0
+
+/* DMA2_ADDR Field */
+#define DMA2_ADDR_MASK				0xFFFFFFFF
+#define DMA2_ADDR_SHIFT			0
+#define DMA2_ADDR_DMA2_ADDR_MASK		0xFFFFFFFF
+#define DMA2_ADDR_DMA2_ADDR_SHIFT		0
+
+/* DMA_CONFIG Field */
+#define DMA_CONFIG_MASK			0xFFFFFFFF
+#define DMA_CONFIG_SHIFT			0
+#define DMA_CONFIG_DMA1_CNT_MASK		0xFFF00000
+#define DMA_CONFIG_DMA1_CNT_SHIFT		20
+#define DMA_CONFIG_DMA2_CNT_MASK		0x000FE000
+#define DMA_CONFIG_DMA2_CNT_SHIFT		13
+#define DMA_CONFIG_DMA2_OFFSET_MASK		0x00001FC0
+#define DMA_CONFIG_DMA2_OFFSET_SHIFT		2
+#define DMA_CONFIG_DMA1_ACT_MASK		0x00000002
+#define DMA_CONFIG_DMA1_ACT_SHIFT		1
+#define DMA_CONFIG_DMA2_ACT_MASK		0x00000001
+#define DMA_CONFIG_DMA2_ACT_SHIFT		0
+
+/* NFC_CACHE_SWAP Field */
+#define CACHE_SWAP_MASK			0x0FFE0FFE
+#define CACHE_SWAP_SHIFT			1
+#define CACHE_SWAP_CACHE_SWAP_ADDR2_MASK	0x0FFE0000
+#define CACHE_SWAP_CACHE_SWAP_ADDR2_SHIFT	17
+#define CACHE_SWAP_CACHE_SWAP_ADDR1_MASK	0x00000FFE
+#define CACHE_SWAP_CACHE_SWAP_ADDR1_SHIFT	1
+
+/* NFC_SECTOR_SIZE Field */
+#define SECTOR_SIZE_MASK			0x00001FFF
+#define SECTOR_SIZE_SHIFT			0
+#define SECTOR_SIZE_SECTOR_SIZE_MASK		0x00001FFF
+#define SECTOR_SIZE_SECTOR_SIZE_SHIFT		0
+
+/* NFC_FLASH_CONFIG Field */
+#define CONFIG_MASK				0xFFFFFFFF
+#define CONFIG_SHIFT				0
+#define CONFIG_STOP_ON_WERR_MASK		0x80000000
+#define CONFIG_STOP_ON_WERR_SHIFT		31
+#define CONFIG_ECC_SRAM_ADDR_MASK		0x7FC00000
+#define CONFIG_ECC_SRAM_ADDR_SHIFT		22
+#define CONFIG_ECC_SRAM_REQ_MASK		0x00200000
+#define CONFIG_ECC_SRAM_REQ_SHIFT		21
+#define CONFIG_DMA_REQ_MASK			0x00100000
+#define CONFIG_DMA_REQ_SHIFT			20
+#define CONFIG_ECC_MODE_MASK			0x000E0000
+#define CONFIG_ECC_MODE_SHIFT			17
+#define CONFIG_FAST_FLASH_MASK			0x00010000
+#define CONFIG_FAST_FLASH_SHIFT		16
+#define CONFIG_ID_COUNT_MASK			0x0000E000
+#define CONFIG_ID_COUNT_SHIFT			13
+#define CONFIG_CMD_TIMEOUT_MASK		0x00001F00
+#define CONFIG_CMD_TIMEOUT_SHIFT		8
+#define CONFIG_16BIT_MASK			0x00000080
+#define CONFIG_16BIT_SHIFT			7
+#define CONFIG_BOOT_MODE_MASK			0x00000040
+#define CONFIG_BOOT_MODE_SHIFT			6
+#define CONFIG_ADDR_AUTO_INCR_MASK		0x00000020
+#define CONFIG_ADDR_AUTO_INCR_SHIFT		5
+#define CONFIG_BUFNO_AUTO_INCR_MASK		0x00000010
+#define CONFIG_BUFNO_AUTO_INCR_SHIFT		4
+#define CONFIG_PAGE_CNT_MASK			0x0000000F
+#define CONFIG_PAGE_CNT_SHIFT			0
+
+/* NFC_IRQ_STATUS Field */
+#define MASK					0xEFFC003F
+#define SHIFT					0
+#define WERR_IRQ_MASK				0x80000000
+#define WERR_IRQ_SHIFT				31
+#define CMD_DONE_IRQ_MASK			0x40000000
+#define CMD_DONE_IRQ_SHIFT			30
+#define IDLE_IRQ_MASK				0x20000000
+#define IDLE_IRQ_SHIFT				29
+#define WERR_STATUS_MASK			0x08000000
+#define WERR_STATUS_SHIFT			27
+#define FLASH_CMD_BUSY_MASK			0x04000000
+#define FLASH_CMD_BUSY_SHIFT			26
+#define RESIDUE_BUSY_MASK			0x02000000
+#define RESIDUE_BUSY_SHIFT			25
+#define ECC_BUSY_MASK				0x01000000
+#define ECC_BUSY_SHIFT				24
+#define DMA_BUSY_MASK				0x00800000
+#define DMA_BUSY_SHIFT				23
+#define WERR_EN_MASK				0x00400000
+#define WERR_EN_SHIFT				22
+#define CMD_DONE_EN_MASK			0x00200000
+#define CMD_DONE_EN_SHIFT			21
+#define IDLE_EN_MASK				0x00100000
+#define IDLE_EN_SHIFT				20
+#define WERR_CLEAR_MASK			0x00080000
+#define WERR_CLEAR_SHIFT			19
+#define CMD_DONE_CLEAR_MASK			0x00040000
+#define CMD_DONE_CLEAR_SHIFT			18
+#define IDLE_CLEAR_MASK			0x00020000
+#define IDLE_CLEAR_SHIFT			17
+#define RESIDUE_BUFF_NO_MASK			0x00000030
+#define RESIDUE_BUFF_NO_SHIFT			4
+#define ECC_BUFF_NO_MASK			0x000000C0
+#define ECC_BUFF_NO_SHIFT			2
+#define DMA_BUFF_NO_MASK			0x00000003
+
+#define NFC_CONFIG_VALUE	(0x0000a632|(ECC_60_BYTE<<17))
+#endif /* MPC5125_NFC_H */
+
diff --git a/include/mpc512x.h b/include/mpc512x.h
index 0f022939da6..f18c4ffe69c 100644
--- a/include/mpc512x.h
+++ b/include/mpc512x.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2006, 2008-2009 Freescale Semiconductor, Inc. All right reserved.
  * (C) Copyright 2007 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
@@ -46,6 +46,7 @@
 #define LPCS6AW			0x003C
 #define LPCA7AW			0x0040
 #define SRAMBAR			0x00C4
+#define NFCBAR			0x00C8
 #define LAWBAR_BAR		0xFFFFF000	/* Base address mask */
 
 #define LPC_OFFSET		0x10000
@@ -70,6 +71,7 @@
 #define SPRIDR_REVID		0x0000FFFF	/* Revision Identification */
 
 #define SPR_5121E		0x80180000
+#define SPR_5125		0x80190000
 
 /* SPCR - System Priority Configuration Register
  */
@@ -211,25 +213,28 @@
 #define CLOCK_SCCR1_PSC_EN(cn)		(0x08000000 >> (cn))
 #define CLOCK_SCCR1_PSCFIFO_EN		0x00008000
 #define CLOCK_SCCR1_SATA_EN		0x00004000
-#define CLOCK_SCCR1_FEC_EN		0x00002000
+#define CLOCK_SCCR1_FEC1_EN		0x00002000
 #define CLOCK_SCCR1_TPR_EN		0x00001000
 #define CLOCK_SCCR1_PCI_EN		0x00000800
 #define CLOCK_SCCR1_DDR_EN		0x00000400
+#define CLOCK_SCCR1_FEC2_EN		0x00000200
 
 /* System Clock Control Register 2 commands */
 #define CLOCK_SCCR2_DIU_EN		0x80000000
 #define CLOCK_SCCR2_AXE_EN		0x40000000
 #define CLOCK_SCCR2_MEM_EN		0x20000000
-#define CLOCK_SCCR2_USB2_EN		0x10000000
-#define CLOCK_SCCR2_USB1_EN		0x08000000
+#define CLOCK_SCCR2_USB1_EN		0x10000000
+#define CLOCK_SCCR2_USB2_EN		0x08000000
 #define CLOCK_SCCR2_I2C_EN		0x04000000
 #define CLOCK_SCCR2_BDLC_EN		0x02000000
-#define CLOCK_SCCR2_SDHC_EN		0x01000000
+#define CLOCK_SCCR2_AUTO_EN		0x02000000
+#define CLOCK_SCCR2_SDHC1_EN		0x01000000
 #define CLOCK_SCCR2_SPDIF_EN		0x00800000
 #define CLOCK_SCCR2_MBX_BUS_EN		0x00400000
 #define CLOCK_SCCR2_MBX_EN		0x00200000
 #define CLOCK_SCCR2_MBX_3D_EN		0x00100000
 #define CLOCK_SCCR2_IIM_EN		0x00080000
+#define CLOCK_SCCR2_SDHC2_EN		0x00020000
 
 /* PSC FIFO Command values */
 #define PSC_FIFO_RESET_SLICE		0x80
@@ -291,10 +296,10 @@
 #define FIFOC_PSC0_RX_SIZE	0x0
 #define FIFOC_PSC0_RX_ADDR	0x0
 
-#define FIFOC_PSC1_TX_SIZE	0x0
-#define FIFOC_PSC1_TX_ADDR	0x0
-#define FIFOC_PSC1_RX_SIZE	0x0
-#define FIFOC_PSC1_RX_ADDR	0x0
+#define FIFOC_PSC1_TX_SIZE	0x04
+#define FIFOC_PSC1_TX_ADDR	0x00
+#define FIFOC_PSC1_RX_SIZE	0x04
+#define FIFOC_PSC1_RX_ADDR	0x04
 
 #define FIFOC_PSC2_TX_SIZE	0x0
 #define FIFOC_PSC2_TX_ADDR	0x0
@@ -302,9 +307,9 @@
 #define FIFOC_PSC2_RX_ADDR	0x0
 
 #define FIFOC_PSC3_TX_SIZE	0x04
-#define FIFOC_PSC3_TX_ADDR	0x0
+#define FIFOC_PSC3_TX_ADDR	0x10
 #define FIFOC_PSC3_RX_SIZE	0x04
-#define FIFOC_PSC3_RX_ADDR	0x10
+#define FIFOC_PSC3_RX_ADDR	0x14
 
 #define FIFOC_PSC4_TX_SIZE	0x0
 #define FIFOC_PSC4_TX_ADDR	0x0
@@ -346,8 +351,271 @@
 #define FIFOC_PSC11_RX_SIZE	0x0
 #define FIFOC_PSC11_RX_ADDR	0x0
 
-/* IO Control Register
- */
+/* MPC5125 */
+#if (BOARD_TYPE==BOARD_TYPE_5125_MPU)
+#define IO_CTRL_MEM		0x00
+#define IO_CTRL_GBOBE		0x01
+#define IO_CTRL_LPC_CLK		0x04
+#define IO_CTRL_LPC_OE_B	0x05
+#define IO_CTRL_LPC_RWB		0x06
+#define IO_CTRL_LPC_CS0_B	0x07
+#define IO_CTRL_LPC_ACK_B	0x08
+#define IO_CTRL_LPC_AX03	0x09
+#define IO_CTRL_EMB_AX02	0x0a
+#define IO_CTRL_EMB_AX01	0x0b
+#define IO_CTRL_EMB_AX00	0x0c
+#define IO_CTRL_EMB_AD31	0x0d
+#define IO_CTRL_EMB_AD30	0x0e
+#define IO_CTRL_EMB_AD29	0x0f
+#define IO_CTRL_EMB_AD28	0x10
+#define IO_CTRL_EMB_AD27	0x11
+#define IO_CTRL_EMB_AD26	0x12
+#define IO_CTRL_EMB_AD25	0x13
+#define IO_CTRL_EMB_AD24	0x14
+#define IO_CTRL_EMB_AD23	0x15
+#define IO_CTRL_EMB_AD22	0x16
+#define IO_CTRL_EMB_AD21	0x17
+#define IO_CTRL_EMB_AD20	0x18
+#define IO_CTRL_EMB_AD19	0x19
+#define IO_CTRL_EMB_AD18	0x1a
+#define IO_CTRL_EMB_AD17	0x1b
+#define IO_CTRL_EMB_AD16	0x1c
+#define IO_CTRL_EMB_AD15	0x1d
+#define IO_CTRL_EMB_AD14	0x1e
+#define IO_CTRL_EMB_AD13	0x1f
+#define IO_CTRL_EMB_AD12	0x20
+#define IO_CTRL_EMB_AD11	0x21
+#define IO_CTRL_EMB_AD10	0x22
+#define IO_CTRL_EMB_AD09	0x23
+#define IO_CTRL_EMB_AD08	0x24
+#define IO_CTRL_EMB_AD07	0x25
+#define IO_CTRL_EMB_AD06	0x26
+#define IO_CTRL_EMB_AD05	0x27
+#define IO_CTRL_EMB_AD04	0x28
+#define IO_CTRL_EMB_AD03	0x29
+#define IO_CTRL_EMB_AD02	0x2a
+#define IO_CTRL_EMB_AD01	0x2b
+#define IO_CTRL_EMB_AD00	0x2c
+#define IO_CTRL_NFC_CE0_B	0x2d
+#define IO_CTRL_NFC_RB		0x2e
+#define IO_CTRL_DIU_CLK		0x2f
+#define IO_CTRL_DIU_DE		0x30
+#define IO_CTRL_DIU_HSYNC	0x31
+#define IO_CTRL_DIU_VSYNC	0x32
+#define IO_CTRL_DIU_LD00	0x33
+#define IO_CTRL_DIU_LD01	0x34
+#define IO_CTRL_DIU_LD02	0x35
+#define IO_CTRL_DIU_LD03	0x36
+#define IO_CTRL_DIU_LD04	0x37
+#define IO_CTRL_DIU_LD05	0x38
+#define IO_CTRL_DIU_LD06	0x39
+#define IO_CTRL_DIU_LD07	0x3a
+#define IO_CTRL_DIU_LD08	0x3b
+#define IO_CTRL_DIU_LD09	0x3c
+#define IO_CTRL_DIU_LD10	0x3d
+#define IO_CTRL_DIU_LD11	0x3e
+#define IO_CTRL_DIU_LD12	0x3f
+#define IO_CTRL_DIU_LD13	0x40
+#define IO_CTRL_DIU_LD14	0x41
+#define IO_CTRL_DIU_LD15	0x42
+#define IO_CTRL_DIU_LD16	0x43
+#define IO_CTRL_DIU_LD17	0x44
+#define IO_CTRL_DIU_LD18	0x45
+#define IO_CTRL_DIU_LD19	0x46
+#define IO_CTRL_DIU_LD20	0x47
+#define IO_CTRL_DIU_LD21	0x48
+#define IO_CTRL_DIU_LD22	0x49
+#define IO_CTRL_DIU_LD23	0x4a
+#define IO_CTRL_CAN4_RX		0x4b
+#define IO_CTRL_CAN4_TX		0x4c
+#define IO_CTRL_CAN1_TX		0x4d
+#define IO_CTRL_CAN2_TX		0x4e
+#define IO_CTRL_I2C1_SCL	0x4f
+#define IO_CTRL_I2C1_SDA	0x50
+#define IO_CTRL_FEC1_TXD_2	0x51
+#define IO_CTRL_FEC1_TXD_3	0x52
+#define IO_CTRL_FEC1_RXD_2	0x53
+#define IO_CTRL_FEC1_RXD_3	0x54
+#define IO_CTRL_FEC1_CRS	0x55
+#define IO_CTRL_FEC1_TX_ER	0x56
+#define IO_CTRL_FEC1_RXD_1	0x57
+#define IO_CTRL_FEC1_TXD_1	0x58
+#define IO_CTRL_FEC1_MDC	0x59
+#define IO_CTRL_FEC1_RX_ER	0x5a
+#define IO_CTRL_FEC1_MDIO	0x5b
+#define IO_CTRL_FEC1_RXD_0	0x5c
+#define IO_CTRL_FEC1_TXD_0	0x5d
+#define IO_CTRL_FEC1_TX_CLK	0x5e
+#define IO_CTRL_FEC1_RX_CLK	0x5f
+#define IO_CTRL_FEC1_RX_DV	0x60
+#define IO_CTRL_FEC1_TX_EN	0x61
+#define IO_CTRL_FEC1_COL	0x62
+#define IO_CTRL_USB1_DATA0	0x63
+#define IO_CTRL_USB1_DATA1	0x64
+#define IO_CTRL_USB1_DATA2	0x65
+#define IO_CTRL_USB1_DATA3	0x66
+#define IO_CTRL_USB1_DATA4	0x67
+#define IO_CTRL_USB1_DATA5	0x68
+#define IO_CTRL_USB1_DATA6	0x69
+#define IO_CTRL_USB1_DATA7	0x6a
+#define IO_CTRL_USB1_STOP	0x6b
+#define IO_CTRL_USB1_CLK	0x6c
+#define IO_CTRL_USB1_NEXT	0x6d
+#define IO_CTRL_USB1_DIR	0x6e
+#define IO_CTRL_SDHC1_CLK	0x6f
+#define IO_CTRL_SDHC1_CMD	0x70
+#define IO_CTRL_SDHC1_D0	0x71
+#define IO_CTRL_SDHC1_D1	0x72
+#define IO_CTRL_SDHC1_D2	0x73
+#define IO_CTRL_SDHC1_D3	0x74
+#define IO_CTRL_PSC_MCLK_IN	0x75
+#define IO_CTRL_PSC0_0		0x76
+#define IO_CTRL_PSC0_1		0x77
+#define IO_CTRL_PSC0_2		0x78
+#define IO_CTRL_PSC0_3		0x79
+#define IO_CTRL_PSC0_4		0x7a
+#define IO_CTRL_PSC1_0		0x7b
+#define IO_CTRL_PSC1_1		0x7c
+#define IO_CTRL_PSC1_2		0x7d
+#define IO_CTRL_PSC1_3		0x7e
+#define IO_CTRL_PSC1_4		0x7f
+#define IO_CTRL_J1850_TX	0x80
+#define IO_CTRL_J1850_RX	0x81
+
+#if 1
+#define IOCTL_MEM		0x00
+#define IOCTL_GBOBE		0x01
+#define IOCTL_LPC_CLK		0x04
+#define IOCTL_LPC_OE_B		0x05
+#define IOCTL_LPC_RWB		0x06
+#define IOCTL_LPC_CS0_B	0x07
+#define IOCTL_LPC_ACK_B	0x08
+#define IOCTL_LPC_AX03		0x09
+#define IOCTL_EMB_AX02		0x0a
+#define IOCTL_EMB_AX01		0x0b
+#define IOCTL_EMB_AX00		0x0c
+#define IOCTL_EMB_AD31		0x0d
+#define IOCTL_EMB_AD30		0x0e
+#define IOCTL_EMB_AD29		0x0f
+#define IOCTL_EMB_AD28		0x10
+#define IOCTL_EMB_AD27		0x11
+#define IOCTL_EMB_AD26		0x12
+#define IOCTL_EMB_AD25		0x13
+#define IOCTL_EMB_AD24		0x14
+#define IOCTL_EMB_AD23		0x15
+#define IOCTL_EMB_AD22		0x16
+#define IOCTL_EMB_AD21		0x17
+#define IOCTL_EMB_AD20		0x18
+#define IOCTL_EMB_AD19		0x19
+#define IOCTL_EMB_AD18		0x1a
+#define IOCTL_EMB_AD17		0x1b
+#define IOCTL_EMB_AD16		0x1c
+#define IOCTL_EMB_AD15		0x1d
+#define IOCTL_EMB_AD14		0x1e
+#define IOCTL_EMB_AD13		0x1f
+#define IOCTL_EMB_AD12		0x20
+#define IOCTL_EMB_AD11		0x21
+#define IOCTL_EMB_AD10		0x22
+#define IOCTL_EMB_AD09		0x23
+#define IOCTL_EMB_AD08		0x24
+#define IOCTL_EMB_AD07		0x25
+#define IOCTL_EMB_AD06		0x26
+#define IOCTL_EMB_AD05		0x27
+#define IOCTL_EMB_AD04		0x28
+#define IOCTL_EMB_AD03		0x29
+#define IOCTL_EMB_AD02		0x2a
+#define IOCTL_EMB_AD01		0x2b
+#define IOCTL_EMB_AD00		0x2c
+#define IOCTL_NFC_CE0_B	0x2d
+#define IOCTL_NFC_RB		0x2e
+#define IOCTL_DIU_CLK		0x2f
+#define IOCTL_DIU_DE		0x30
+#define IOCTL_DIU_HSYNC	0x31
+#define IOCTL_DIU_VSYNC	0x32
+#define IOCTL_DIU_LD00		0x33
+#define IOCTL_DIU_LD01		0x34
+#define IOCTL_DIU_LD02		0x35
+#define IOCTL_DIU_LD03		0x36
+#define IOCTL_DIU_LD04		0x37
+#define IOCTL_DIU_LD05		0x38
+#define IOCTL_DIU_LD06		0x39
+#define IOCTL_DIU_LD07		0x3a
+#define IOCTL_DIU_LD08		0x3b
+#define IOCTL_DIU_LD09		0x3c
+#define IOCTL_DIU_LD10		0x3d
+#define IOCTL_DIU_LD11		0x3e
+#define IOCTL_DIU_LD12		0x3f
+#define IOCTL_DIU_LD13		0x40
+#define IOCTL_DIU_LD14		0x41
+#define IOCTL_DIU_LD15		0x42
+#define IOCTL_DIU_LD16		0x43
+#define IOCTL_DIU_LD17		0x44
+#define IOCTL_DIU_LD18		0x45
+#define IOCTL_DIU_LD19		0x46
+#define IOCTL_DIU_LD20		0x47
+#define IOCTL_DIU_LD21		0x48
+#define IOCTL_DIU_LD22		0x49
+#define IOCTL_DIU_LD23		0x4a
+#define IOCTL_I2C2_SCL		0x4b
+#define IOCTL_I2C2_SDA		0x4c
+#define IOCTL_CAN1_TX		0x4d
+#define IOCTL_CAN2_TX		0x4e
+#define IOCTL_I2C1_SCL		0x4f
+#define IOCTL_I2C1_SDA		0x50
+#define IOCTL_FEC1_TXD_2	0x51
+#define IOCTL_FEC1_TXD_3	0x52
+#define IOCTL_FEC1_RXD_2	0x53
+#define IOCTL_FEC1_RXD_3	0x54
+#define IOCTL_FEC1_CRS		0x55
+#define IOCTL_FEC1_TX_ER	0x56
+#define IOCTL_FEC1_RXD_1	0x57
+#define IOCTL_FEC1_TXD_1	0x58
+#define IOCTL_FEC1_MDC		0x59
+#define IOCTL_FEC1_RX_ER	0x5a
+#define IOCTL_FEC1_MDIO	0x5b
+#define IOCTL_FEC1_RXD_0	0x5c
+#define IOCTL_FEC1_TXD_0	0x5d
+#define IOCTL_FEC1_TX_CLK	0x5e
+#define IOCTL_FEC1_RX_CLK	0x5f
+#define IOCTL_FEC1_RX_DV	0x60
+#define IOCTL_FEC1_TX_EN	0x61
+#define IOCTL_FEC1_COL		0x62
+#define IOCTL_USB1_DATA0	0x63
+#define IOCTL_USB1_DATA1	0x64
+#define IOCTL_USB1_DATA2	0x65
+#define IOCTL_USB1_DATA3	0x66
+#define IOCTL_USB1_DATA4	0x67
+#define IOCTL_USB1_DATA5	0x68
+#define IOCTL_USB1_DATA6	0x69
+#define IOCTL_USB1_DATA7	0x6a
+#define IOCTL_USB1_STOP	0x6b
+#define IOCTL_USB1_CLK		0x6c
+#define IOCTL_USB1_NEXT	0x6d
+#define IOCTL_USB1_DIR		0x6e
+#define IOCTL_SDHC1_CLK	0x6f
+#define IOCTL_SDHC1_CMD	0x70
+#define IOCTL_SDHC1_D0		0x71
+#define IOCTL_SDHC1_D1		0x72
+#define IOCTL_SDHC1_D2		0x73
+#define IOCTL_SDHC1_D3		0x74
+#define IOCTL_PSC_MCLK_IN	0x75
+#define IOCTL_PSC0_0		0x76
+#define IOCTL_PSC0_1		0x77
+#define IOCTL_PSC0_2		0x78
+#define IOCTL_PSC0_3		0x79
+#define IOCTL_PSC0_4		0x7a
+#define IOCTL_PSC1_0		0x7b
+#define IOCTL_PSC1_1		0x7c
+#define IOCTL_PSC1_2		0x7d
+#define IOCTL_PSC1_3		0x7e
+#define IOCTL_PSC1_4		0x7f
+#define IOCTL_J1850_TX		0x80
+#define IOCTL_J1850_RX		0x81
+#endif
+
+
+#else
+/* MPC5121 */
 #define IOCTL_MEM		0x000
 #define IOCTL_GP		0x004
 #define IOCTL_LPC_CLK		0x008
@@ -545,12 +813,16 @@
 #define IOCTL_USB2_VBUS_PWR_FAULT	0x308
 #define IOCTL_USB2_VBUS_PWR_SELECT	0x30C
 #define IOCTL_USB2_PHY_DRVV_BUS		0x310
-
+#endif
 #ifndef __ASSEMBLY__
 
 
 /* IO pin fields */
+#ifdef CONFIG_ADS5125
+#define IO_PIN_FMUX(v)	((v) << 5)	/* pin function */
+#else
 #define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
+#endif
 #define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
 #define IO_PIN_PUD(v)	((v) << 4)	/* if PUE, 0=pull-down, 1=pull-up */
 #define IO_PIN_PUE(v)	((v) << 3)	/* pull up/down enable */
@@ -561,7 +833,12 @@ typedef struct iopin_t {
 	int p_offset;		/* offset from IOCTL_MEM_OFFSET */
 	int nr_pins;		/* number of pins to set this way */
 	int bit_or;		/* or in the value instead of overwrite */
+#ifdef CONFIG_ADS5125
+	u_char val;
+	u_char res0[3];
+#else
 	u_long val;		/* value to write or or */
+#endif
 }iopin_t;
 
 void iopin_initialize(iopin_t *,int);
@@ -569,7 +846,7 @@ void iopin_initialize(iopin_t *,int);
 
 /* Indexes in regs array */
 /* Set for DDR */
-#define IOCTRL_MUX_DDR		0x00000036
+#define IOCTRL_MUX_DDR		0x00000000
 
  /* Register Offset Base */
 #define MPC512X_FEC		(CONFIG_SYS_IMMR + 0x02800)