diff options
| author | Ye Li <ye.li@nxp.com> | 2019-03-18 20:54:06 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-04-06 18:02:56 +0800 |
| commit | 6b5759ed99f03a63598be09c5ff57f6540b33d65 (patch) | |
| tree | 64b52aa99b950bc613e04780c270675a7a5e1f95 /include | |
| parent | e9c4400e36cca0d550246f2558b927e501918c14 (diff) | |
MLK-21830-1 imx8qm: Update soc codes for iMX8QM
Add CPU type, Kconfig for iMX8QM and update SoC codes.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 3512fc146095df33882ae45a62174924b7aac58c)
(cherry picked from commit 1d5b77f78c09e572975e722b3ed908e6becdf337)
(cherry picked from commit f73c232781239c5f54148b5da2061a173eb6a583)
(cherry picked from commit 8e1aa344a731d47fc12dc5be3105b0fa0ceecf5a)
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/imx8qm-clock.h | 8 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/pads-imx8qm.h | 36 |
2 files changed, 36 insertions, 8 deletions
diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h index 58de976e638..d87ff262bc6 100644 --- a/include/dt-bindings/clock/imx8qm-clock.h +++ b/include/dt-bindings/clock/imx8qm-clock.h @@ -841,6 +841,12 @@ #define IMX8QM_AUD_DSP_CORE_CLK 794 #define IMX8QM_AUD_OCRAM_IPG 795 -#define IMX8QM_CLK_END 796 +/* MIPI DSI */ +#define IMX8QM_MIPI0_DSI_PHY_DIV 796 +#define IMX8QM_MIPI0_DSI_PHY_CLK 797 +#define IMX8QM_MIPI1_DSI_PHY_DIV 798 +#define IMX8QM_MIPI1_DSI_PHY_CLK 799 + +#define IMX8QM_CLK_END 800 #endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h index e980fd55ede..5416669f035 100644 --- a/include/dt-bindings/pinctrl/pads-imx8qm.h +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -275,13 +275,11 @@ #define SC_P_ENET1_RGMII_RXD2 266 /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ #define SC_P_ENET1_RGMII_RXD3 267 /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */ #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /* */ -/*@}*/ -/*! - * @name Pad Mux Definitions +/* + * Pad Mux Definitions * format: name padid padmux */ -/*@{*/ #define SC_P_SIM0_CLK_DMA_SIM0_CLK SC_P_SIM0_CLK 0 #define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 SC_P_SIM0_CLK 3 #define SC_P_SIM0_RST_DMA_SIM0_RST SC_P_SIM0_RST 0 @@ -955,7 +953,31 @@ #define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1 #define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2 #define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3 -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 -#endif /* SC_PADS_H */ +/* + * Fake Pad Mux Definitions + * format: name padid 0 + */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO_PAD SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 0 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 + +#endif /* SC_PADS_H */ |