diff options
| author | Tom Rini <trini@konsulko.com> | 2022-02-21 08:32:02 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-02-21 08:32:02 -0500 |
| commit | 24b628a8f844868adca897aae40af6f98cdbc26d (patch) | |
| tree | 43572009123231107d618dce3a4f84d7e2c536d6 /include | |
| parent | 55e9cef1432ffd42559874b2a469729f20b627d9 (diff) | |
| parent | 9bd4232f958b94fdd700e44897fb61bdc898b787 (diff) | |
Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.04-rc3
microblaze:
- Fix exception handler
zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot
xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection
power:
- Add zynqmp power management driver
scsi:
- Add phy support to ceva driver
zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations
net:
- Fix 64bit calculation in axi_emac
video:
- Add missing gpio dependency for seps driver
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/microblaze-generic.h | 3 | ||||
| -rw-r--r-- | include/zynqmp_firmware.h | 47 |
2 files changed, 40 insertions, 10 deletions
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index ca749ed18ac..fd5a9cf8b8e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -11,9 +11,6 @@ /* Microblaze is microblaze_0 */ #define XILINX_FSL_NUMBER 3 -/* MicroBlaze CPU */ -#define MICROBLAZE_V5 1 - #define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* uart */ diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 0b068d7da29..50bf4ef3953 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -342,20 +342,20 @@ enum pm_ioctl_id { IOCTL_AIE_ISR_CLEAR = 24, }; -#define PM_SIP_SVC 0xc2000000 +#define PM_SIP_SVC 0xc2000000 -#define ZYNQMP_PM_VERSION_MAJOR 1 -#define ZYNQMP_PM_VERSION_MINOR 0 -#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 -#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF +#define ZYNQMP_PM_VERSION_MAJOR 1 +#define ZYNQMP_PM_VERSION_MINOR 0 +#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 +#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF #define ZYNQMP_PM_VERSION \ ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ ZYNQMP_PM_VERSION_MINOR) -#define ZYNQMP_PM_VERSION_INVALID ~0 +#define ZYNQMP_PM_VERSION_INVALID ~0 -#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) +#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) /* * Return payload size @@ -367,8 +367,41 @@ enum pm_ioctl_id { #define PAYLOAD_ARG_CNT 5U unsigned int zynqmp_firmware_version(void); +int zynqmp_pmufw_node(u32 id); +int zynqmp_pmufw_config_close(void); void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); +/* Type of Config Object */ +#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U +#define PM_CONFIG_OBJECT_TYPE_OVERLAY 0x2U + +/* Section Id */ +#define PM_CONFIG_SLAVE_SECTION_ID 0x102U +#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U + +/* Flag Option */ +#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U +#define PM_MASTER_USING_SLAVE_MASK 0x2U + +/* IPI Mask for Master */ +#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001 +#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100 +#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200 + +enum zynqmp_pm_request_ack { + ZYNQMP_PM_REQUEST_ACK_NO = 1, + ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2, + ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3, +}; + +/* Node capabilities */ +#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U +#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U +#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U +#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U + +#define ZYNQMP_PM_MAX_QOS 100U + #endif /* _ZYNQMP_FIRMWARE_H_ */ |