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authorÁlvaro Fernández Rojas <noltari@gmail.com>2017-05-03 15:10:24 +0200
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2017-05-10 16:16:09 +0200
commit02bb1fa09ed4caec6d2aa6565fac62087016b306 (patch)
tree9afada6ed189f12331fa22d40a59f06e66d44c9d /include
parent78118211fb61df2f6427dc0ea7a65c97c20b3d11 (diff)
mips: bmips: add bcm6345-rst driver support for BCM63268
This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/reset/bcm63268-reset.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h
new file mode 100644
index 00000000000..1373884b361
--- /dev/null
+++ b/include/dt-bindings/reset/bcm63268-reset.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM63268_H
+#define __DT_BINDINGS_RESET_BCM63268_H
+
+#define BCM63268_RST_SPI 0
+#define BCM63268_RST_IPSEC 1
+#define BCM63268_RST_EPHY 2
+#define BCM63268_RST_SAR 3
+#define BCM63268_RST_ENETSW 4
+#define BCM63268_RST_USBS 5
+#define BCM63268_RST_USBH 6
+#define BCM63268_RST_PCM 7
+#define BCM63268_RST_PCIE_CORE 8
+#define BCM63268_RST_PCIE 9
+#define BCM63268_RST_PCIE_EXT 10
+#define BCM63268_RST_WLAN_SHIM 11
+#define BCM63268_RST_DDR_PHY 12
+#define BCM63268_RST_FAP0 13
+#define BCM63268_RST_WLAN_UBUS 14
+#define BCM63268_RST_DECT 15
+#define BCM63268_RST_FAP1 16
+#define BCM63268_RST_PCIE_HARD 17
+#define BCM63268_RST_GPHY 18
+
+#endif /* __DT_BINDINGS_RESET_BCM63268_H */