diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2018-04-11 17:07:45 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-08 09:07:34 -0400 |
| commit | 8b41464547330a39cc7e0ef87a5dd8f34db324e1 (patch) | |
| tree | ea0eb1eb7e28a3dba811bed5f1532a3acc2e296a /include/stm32_rcc.h | |
| parent | 274fb461f4792431b3777874472c8bd6149e6168 (diff) | |
clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock
On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested By: Bruno Herrera <bruherrera@gmail.com>
Diffstat (limited to 'include/stm32_rcc.h')
| -rw-r--r-- | include/stm32_rcc.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h index 748c2ebd0c9..71da3c1a871 100644 --- a/include/stm32_rcc.h +++ b/include/stm32_rcc.h @@ -40,7 +40,8 @@ struct stm32_clk_info { }; enum soc_family { - STM32F4, + STM32F42X, + STM32F469, STM32F7, }; |