diff options
| author | Niklaus Giger <niklaus.giger@member.fsf.org> | 2009-10-04 20:04:19 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-07 09:15:13 +0200 |
| commit | f80e61dcfe53fa3a5936659883415c9bd1b5a3d9 (patch) | |
| tree | 0ba42dd2d01d33da0e0fcd2ed816b70f1fbc1f36 /include/ppc440.h | |
| parent | 56f14818f66c68a8b9e45925f29ceb974405ad48 (diff) | |
ppc4xx: Cleanup some HW register names
Here you find all the changes in the include directory for new register names
and adapting other ones to the names used by AMCC in their manuals, e.g.
For 440EPx/GRPPC440EPx/GRX, Revision 1.15 – September 22, 2008
For PPC405GP Embedded Processor, Revision 1.02 – March 22, 2006
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 179 |
1 files changed, 99 insertions, 80 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index 378a9de20a6..9299a7172a3 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -60,9 +60,9 @@ /* values for clkcfga register - indirect addressing of these regs */ #define CPR0_PLLC 0x0040 #define CPR0_PLLD 0x0060 -#define CPR0_PRIMAD 0x0080 -#define CPR0_PRIMBD 0x00a0 -#define CPR0_OPBD 0x00c0 +#define CPR0_PRIMAD0 0x0080 +#define CPR0_PRIMBD0 0x00a0 +#define CPR0_OPBD0 0x00c0 #define CPR0_PERD 0x00e0 #define CPR0_MALD 0x0100 #define CPR0_SPCID 0x0120 @@ -100,7 +100,7 @@ #define SDR0_PFC1 0x4101 /* Pin Function 1 */ #define SDR0_MFR 0x4300 /* SDR0_MFR reg */ -#ifdef CONFIG_440GX +#if defined(CONFIG_440GX) #define SD0_AMP 0x0240 #define SDR0_XPLLC 0x01c1 #define SDR0_XPLLD 0x01c2 @@ -1319,6 +1319,19 @@ #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ #endif + +#if defined(CONFIG_440EPX) +#define CPM0_ER 0x000000B0 +#define CPM1_ER 0x000000F0 +#define PLB4A0_ACR 0x00000081 +#define PLB4A1_ACR 0x00000089 +#define PLB3A0_ACR 0x00000077 +#define OPB2PLB40_BCTRL 0x00000350 +#define P4P3BO0_CFG 0x00000026 +#define SPI0_MODE 0xEF600090 /* SPI Mode Regsgiter */ + +#endif + #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) @@ -1385,6 +1398,12 @@ #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ +#define SDR0_EMAC0RXST 0x00004301 /* */ +#define SDR0_EMAC0TXST 0x00004302 /* */ +#define SDR0_CRYP0 0x00004500 +#define SDR0_EBC0 0x00000100 +#define SDR0_SDSTP2 0x00004001 +#define SDR0_SDSTP3 0x00004001 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) #define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ @@ -1586,7 +1605,7 @@ #define IICEXTSTS 0x09 #define IICLSADR 0x0A #define IICHSADR 0x0B -#define IICCLKDIV 0x0C +#define IIC0_CLKDIV 0x0C #define IICINTRMSK 0x0D #define IICXFRCNT 0x0E #define IICXTCNTLSS 0x0F @@ -1595,10 +1614,10 @@ /*----------------------------------------------------------------------------- | PCI Internal Registers et. al. (accessed via plb) +----------------------------------------------------------------------------*/ -#define PCIX0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) -#define PCIX0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004) -#define PCIX0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000) -#define PCIX0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000) +#define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) +#define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004) +#define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000) +#define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -1608,82 +1627,82 @@ #define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ /* PCI Master Local Configuration Registers */ -#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ -#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ -#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ -#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ -#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ -#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ -#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ -#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ -#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ -#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ -#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ -#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ +#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ +#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ +#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ +#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ +#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ +#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ +#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ +#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ +#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ +#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ +#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ +#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ /* PCI Target Local Configuration Registers */ -#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */ -#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ -#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */ -#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ +#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */ +#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ +#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */ +#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ #else -#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID ) -#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID ) -#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND ) -#define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS ) -#define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID ) -#define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE) -#define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE ) -#define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER ) -#define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE ) -#define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST ) -#define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 ) -#define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 ) -#define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 ) -#define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 ) -#define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 ) -#define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 ) -#define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS ) -#define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) -#define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID ) -#define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS ) -#define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST ) -#define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 ) -#define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 ) -#define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 ) -#define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE ) -#define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN ) -#define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT ) -#define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT ) - -#define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040) -#define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044) - -#define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068) -#define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c) -#define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070) -#define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074) -#define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078) -#define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c) -#define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080) -#define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084) -#define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088) -#define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c) -#define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090) - -#define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098) -#define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c) -#define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0) -#define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4) -#define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8) -#define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac) -#define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0) -#define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4) -#define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8) - -#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0) +#define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID ) +#define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID ) +#define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND ) +#define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS ) +#define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID ) +#define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE) +#define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE ) +#define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER ) +#define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE ) +#define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST ) +#define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 ) +#define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 ) +#define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 ) +#define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 ) +#define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 ) +#define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 ) +#define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS ) +#define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) +#define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID ) +#define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS ) +#define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST ) +#define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 ) +#define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 ) +#define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 ) +#define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE ) +#define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN ) +#define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT ) +#define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT ) + +#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) +#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) + +#define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068) +#define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c) +#define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070) +#define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074) +#define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078) +#define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c) +#define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080) +#define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084) +#define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088) +#define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c) +#define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090) + +#define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098) +#define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c) +#define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0) +#define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4) +#define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8) +#define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac) +#define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0) +#define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4) +#define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8) + +#define PCIL0_STS (PCIL0_CFGBASE + 0x00e0) #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */ |