diff options
| author | Heiko Schocher <hs@denx.de> | 2008-11-19 10:10:30 +0100 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2008-11-19 18:43:09 -0600 |
| commit | facdad5f2602e899a01746916beddbf9e856b5ee (patch) | |
| tree | 148730fd3c22dca6fa17f6a60b156ca717b41f9e /include/mpc83xx.h | |
| parent | 2f2a5c3714d17f4ead18b713128b7226e0e822f4 (diff) | |
powerpc: 83xx: add missing TIMING_CFG1_CASLAT_* defines
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/mpc83xx.h')
| -rw-r--r-- | include/mpc83xx.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index a2c0ed9e0c6..43553f5ae65 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -887,7 +887,9 @@ #define TIMING_CFG1_WRTORD_SHIFT 0 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ -#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 2.5 */ +#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ +#define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ +#define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ |