diff options
| author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2008-03-24 20:46:57 +0300 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2008-03-25 19:16:47 -0500 |
| commit | d892b2dbb4087a26778bfd42470c3ea7d0e2b6aa (patch) | |
| tree | 6b64ad8afb812db8a116f1bb38d90146c3e3751a /include/mpc83xx.h | |
| parent | d47d49cc37a38f2719a3e1b9bbe08ac810cf2d9a (diff) | |
mpc83xx: MPC8360E-RDK: rework ddr setup, enable ecc
Current DDR setup easily causes memory corruption, this patch fixes it.
Also fix TIMING_CFG0_MRS_CYC definition.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Diffstat (limited to 'include/mpc83xx.h')
| -rw-r--r-- | include/mpc83xx.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index e84442b7ba2..4ee38aafa94 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -881,7 +881,7 @@ #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 -#define TIMING_CFG0_MRS_CYC 0x00000F00 +#define TIMING_CFG0_MRS_CYC 0x0000000F #define TIMING_CFG0_MRS_CYC_SHIFT 0 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 @@ -904,6 +904,7 @@ #define TIMING_CFG1_WRTORD_SHIFT 0 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ +#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 2.5 */ /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ |