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author | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2023-02-01 10:00:26 +0100 |
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committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2023-11-09 13:09:06 +0100 |
commit | e9130d0d46e56fa1b0f6e3f0a405d4df0e8a6ddb (patch) | |
tree | 92b794fe5d877fd1cc41736a50ca4efc2051d6ae /include/media_bus_format.h | |
parent | ae1be88a21790921adc7b24e591055e4fb642bd4 (diff) |
board: verdin-imx8mp: update DDRC config to support different LPDDR4 memories
Add support to Verdin IMX8MP V1.1B SKU which uses
MT53E1G32D2FW-046 WT:B memory.
Compared to the 8 GB memory (MT53E2G32D4NQ-046 WT:A) used on
Verdin IMX8MP V1.0A it has 16 row addresses instead of 17.
In fact, the new memory, is a 2 GB/rank memory. The 8 GB memory is a
4 GB/rank memory.
Manually tweaking Host Interface addresses vs LPDDR4 signals mapping
it is possible to have a single configuration working with both memories:
- Old configuration: HIF bit 30 -> rank, HIF bit 29 -> Row 16
- New configuration: HIF bit 29 -> rank, HIF bit 30 -> Row 16
With this change the memory space from the host processor is contiguous
for both the configurations and the correct memory size is computed
using get_ram_size() at runtime.
Support for single rank memories still works thanks to the fact
dual ranks training fails (ddr_init->ddr_cfg_phy) toward single rank
memories.
Upstream-Status: Backport[72b912502aef]
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Diffstat (limited to 'include/media_bus_format.h')
0 files changed, 0 insertions, 0 deletions