diff options
| author | Dhruva Gole <d-gole@ti.com> | 2022-11-17 17:40:58 +0530 |
|---|---|---|
| committer | Anand Gadiyar <gadiyar@ti.com> | 2022-11-21 09:33:36 -0600 |
| commit | a9df6cd890da6984504c00d466069b960366395e (patch) | |
| tree | 9f458470b8899c8f06c13386114fb3ce857520dc /include/linux | |
| parent | 35c5ec0da0c43660da065ef87b8486c185920675 (diff) | |
mtd: spi-nor-core: Add support for volatile QE bit
Commit a4aa9b7522dc67745795c1e2a76115a616da00ea upstream.
Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad Enable bit in
CFR1 volatile.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 72e48351cc..74e5348e33 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -125,6 +125,7 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ +#define SPINOR_REG_ADDR_CFR1V 0x00800002 /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ |