diff options
| author | York Sun <yorksun@freescale.com> | 2015-11-04 10:03:17 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-12-13 18:27:27 -0800 |
| commit | 19601dd99c8169e27457a96f03f0c3fef908a4c6 (patch) | |
| tree | ed527dd9f102deeef41114fb021a3fb968a0ba8d /include/fsl_ddr_sdram.h | |
| parent | 5076c64a08d2083af5a7761b12a30116ef0da967 (diff) | |
driver/ddr/fsl: Update DDR4 RTT values
DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_ddr_sdram.h')
| -rw-r--r-- | include/fsl_ddr_sdram.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index c79fce0898..4b022d4639 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -33,6 +33,15 @@ #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ +#define DDR4_RTT_OFF 0 +#define DDR4_RTT_60_OHM 1 /* RZQ/4 */ +#define DDR4_RTT_120_OHM 2 /* RZQ/2 */ +#define DDR4_RTT_40_OHM 3 /* RZQ/6 */ +#define DDR4_RTT_240_OHM 4 /* RZQ/1 */ +#define DDR4_RTT_48_OHM 5 /* RZQ/5 */ +#define DDR4_RTT_80_OHM 6 /* RZQ/3 */ +#define DDR4_RTT_34_OHM 7 /* RZQ/7 */ + #define DDR2_RTT_OFF 0 #define DDR2_RTT_75_OHM 1 #define DDR2_RTT_150_OHM 2 |