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authorShengzhou Liu <Shengzhou.Liu@nxp.com>2016-03-16 13:50:23 +0800
committerYork Sun <york.sun@nxp.com>2016-05-17 09:26:53 -0700
commit5fc62fe57097e195a8047859cd3c278a5d6790b6 (patch)
tree1b22ea733a537daa1866c87543e5cdec7c08d432 /include/fsl_ddr_sdram.h
parent4a68489e12313a7fa8740463dee0eea2985eb563 (diff)
driver/ddr/fsl: Add workaround for erratum A-009801
The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/fsl_ddr_sdram.h')
-rw-r--r--include/fsl_ddr_sdram.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index acddf14a3f..486e47e508 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -189,6 +189,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
/* DEBUG_29 register */
#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */