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author | Tom Warren <twarren@nvidia.com> | 2011-11-16 16:38:34 -0700 |
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committer | Gerrit <chrome-bot@google.com> | 2011-11-18 00:00:45 -0800 |
commit | 318c9b21768d937e4a8984af86fec6fcd02242f2 (patch) | |
tree | 7f76b9915570a9e1d1c8d3cf16d318676ba2764b /include/fdt_decode.h | |
parent | e0a72afdcd769abd7ac3465d86e45bc0ccd95833 (diff) |
arm: Tegra3: complete 408MHz PLLP init
Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=chromium-os:21033
TEST=Built and booted OK on my Waluigi. UART is OK, mmc, spi, i2c OK.
Note that this is only valid with CONFIG_SYS_PLLP_BASE_IS_408MHZ.
No affect on Tegra2. Seaboard builds fine, BTW.
Change-Id: I05a367afd1e78a2170d7308a658ce64017850ca0
Reviewed-on: https://gerrit.chromium.org/gerrit/11811
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Diffstat (limited to 'include/fdt_decode.h')
0 files changed, 0 insertions, 0 deletions