diff options
author | Ryan Chen <ryan_chen@aspeedtech.com> | 2020-08-31 14:03:04 +0800 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2020-09-09 16:57:35 -0400 |
commit | c39c9a94cba01d9fbbe359a8922d2ae85061a4e1 (patch) | |
tree | 2d573c30719bf462d6009ac649f6a3a92782f003 /include/dt-bindings | |
parent | 15b87feb2b7923ef679e9da3f956e7a836fbaa40 (diff) |
clock:aspeed: Sync with Linux kernel clock header define
v2: modify title description aspeed:clock -> clock:aspeed
Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r-- | include/dt-bindings/clock/aspeed-clock.h | 68 |
1 files changed, 40 insertions, 28 deletions
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 4803abe9f62..e6599deeb9f 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -1,30 +1,42 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Google Inc. - */ -/* Core Clocks */ -#define PLL_HPLL 1 -#define PLL_DPLL 2 -#define PLL_D2PLL 3 -#define PLL_MPLL 4 -#define ARMCLK 5 - - -/* Bus Clocks, derived from core clocks */ -#define BCLK_PCLK 101 -#define BCLK_LHCLK 102 -#define BCLK_MACCLK 103 -#define BCLK_SDCLK 104 -#define BCLK_ARMCLK 105 - -#define MCLK_DDR 201 - -/* Special clocks */ -#define PCLK_UART1 501 -#define PCLK_UART2 502 -#define PCLK_UART3 503 -#define PCLK_UART4 504 -#define PCLK_UART5 505 -#define PCLK_MAC1 506 -#define PCLK_MAC2 507 +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK 7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK 12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK 16 +#define ASPEED_CLK_GATE_MAC1CLK 17 +#define ASPEED_CLK_GATE_MAC2CLK 18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL 24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART 27 +#define ASPEED_CLK_SDIO 28 +#define ASPEED_CLK_ECLK 29 +#define ASPEED_CLK_ECLK_MUX 30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK 33 +#define ASPEED_CLK_MPLL 34 +#define ASPEED_CLK_24M 35 +#define ASPEED_CLK_MAC1RCLK 36 +#define ASPEED_CLK_MAC2RCLK 37 +#define ASPEED_CLK_DPLL 38 +#define ASPEED_CLK_D2PLL 39 |