diff options
| author | Andy Duan <fugang.duan@nxp.com> | 2018-08-08 13:16:07 +0800 |
|---|---|---|
| committer | Andy Duan <fugang.duan@nxp.com> | 2018-08-10 15:12:08 +0800 |
| commit | bbfd694dc02ea155a5677b4db1f9ec1f76abce9c (patch) | |
| tree | e5aec326ec158ce29dadbaac58981b64527b84ac /include/dt-bindings | |
| parent | dddd60f948ea0d5b24da7fba3c49085aa3b8f02d (diff) | |
MLK-19189 arm64: dts: imx8qm/qxp: set enet IO voltage to 1.8v
By default, imx8qm/qxp b0 silicon set the IO voltage to 2.5v, but mek/arm2
boards are designed as 1.8v voltage for enet IO, so force the IO voltage
to 1.8 by setting COMP_CTL_GPIO_1V8_3V3 pins like:
The pin setting:
1.8V/3.3V : bit4=0, bit[30]=1, bit[2:0]=000
2.5V : bit4=1, bit[30]=1, bit[2:0]=010
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/pinctrl/pads-imx8qm.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/pads-imx8qxp.h | 3 |
2 files changed, 5 insertions, 0 deletions
diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h index ba75ecb7a56..0be7c192a2c 100644 --- a/include/dt-bindings/pinctrl/pads-imx8qm.h +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -969,6 +969,8 @@ #define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1 #define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2 #define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 /*@}*/ #endif /* SC_PADS_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h index 80497358419..05c67091dc9 100644 --- a/include/dt-bindings/pinctrl/pads-imx8qxp.h +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -764,6 +764,9 @@ #define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1 #define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2 #define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 /*@}*/ #endif /* SC_PADS_H */ |