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| author | Tom Rini <trini@konsulko.com> | 2017-11-29 08:26:07 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-11-29 08:26:07 -0500 |
| commit | b06c46de632c55f4c39d404c6f0f65e414b31050 (patch) | |
| tree | dea1702529c8d33c5e70eb5eb6ecf7d08eed23b9 /include/dt-bindings | |
| parent | fcc8250c2f7c982f3593a8eecf737f8e2c95f222 (diff) | |
| parent | a04a5daae25a74ad2ac90b66667dac126242baa0 (diff) | |
Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.1
Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling
ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board
Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h new file mode 100644 index 0000000000..e1b81fe5ef --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -0,0 +1,30 @@ +/* + * MIO pin configuration defines for Xilinx ZynqMP + * + * Copyright (C) 2017 Xilinx, Inc. + * Author: Chirag Parekh <chirag.parekh@xilinx.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H +#define _DT_BINDINGS_PINCTRL_ZYNQMP_H + +/* Bit value for IO standards */ +#define IO_STANDARD_LVCMOS33 0 +#define IO_STANDARD_LVCMOS18 1 + +/* Bit values for Slew Rates */ +#define SLEW_RATE_FAST 0 +#define SLEW_RATE_SLOW 1 + +/* Bit values for Pin inputs */ +#define PIN_INPUT_TYPE_CMOS 0 +#define PIN_INPUT_TYPE_SCHMITT 1 + +#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ |