diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2017-12-10 21:20:08 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2017-12-11 11:36:23 +0300 |
| commit | e80dac0ab83ccb1d54e2d91b93d27b54a7f6544f (patch) | |
| tree | 9d4f6ad7ca865c4b7a01f3b0ebd19c047cf6230d /include/dt-bindings | |
| parent | 3cf239394a5ca3ada68c683ef5d19e16f9bfd170 (diff) | |
ARC: clk: introduce HSDK CGU clock driver
Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.
Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/snps,hsdk-cgu.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h b/include/dt-bindings/clock/snps,hsdk-cgu.h new file mode 100644 index 0000000000..813ab71531 --- /dev/null +++ b/include/dt-bindings/clock/snps,hsdk-cgu.h @@ -0,0 +1,40 @@ +/* + * Synopsys HSDK SDP CGU clock driver dts bindings + * + * Copyright (C) 2017 Synopsys + * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_ +#define __DT_BINDINGS_CLK_HSDK_CGU_H_ + +#define CLK_ARC_PLL 0 +#define CLK_ARC 1 +#define CLK_DDR_PLL 2 +#define CLK_SYS_PLL 3 +#define CLK_SYS_APB 4 +#define CLK_SYS_AXI 5 +#define CLK_SYS_ETH 6 +#define CLK_SYS_USB 7 +#define CLK_SYS_SDIO 8 +#define CLK_SYS_HDMI 9 +#define CLK_SYS_GFX_CORE 10 +#define CLK_SYS_GFX_DMA 11 +#define CLK_SYS_GFX_CFG 12 +#define CLK_SYS_DMAC_CORE 13 +#define CLK_SYS_DMAC_CFG 14 +#define CLK_SYS_SDIO_REF 15 +#define CLK_SYS_SPI_REF 16 +#define CLK_SYS_I2C_REF 17 +#define CLK_SYS_UART_REF 18 +#define CLK_SYS_EBI_REF 19 +#define CLK_TUN_PLL 20 +#define CLK_TUN 21 +#define CLK_HDMI_PLL 22 +#define CLK_HDMI 23 + +#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */ |