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authorJim Liu <jim.t90615@gmail.com>2022-04-19 13:32:20 +0800
committerTom Rini <trini@konsulko.com>2022-05-05 09:28:47 -0400
commitc7554574ff1532983149ab6d7351896d1010b14e (patch)
tree8647241aba7016e3c8b66c88dfcc21e654fdb666 /include/dt-bindings/clock
parent84335544ead850efa80139cf9aa8e83eb6bfdfb4 (diff)
clk: nuvoton: Add support for NPCM750
Add clock controller driver for NPCM750 Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r--include/dt-bindings/clock/nuvoton,npcm7xx-clock.h46
1 files changed, 46 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
new file mode 100644
index 0000000000..65e6bc4eee
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Nuvoton NPCM7xx Clock Generator binding
+ * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
+ *
+ * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
+#define __DT_BINDINGS_CLOCK_NPCM7XX_H
+
+#define NPCM7XX_CLK_CPU 0
+#define NPCM7XX_CLK_GFX_PIXEL 1
+#define NPCM7XX_CLK_MC 2
+#define NPCM7XX_CLK_ADC 3
+#define NPCM7XX_CLK_AHB 4
+#define NPCM7XX_CLK_TIMER 5
+#define NPCM7XX_CLK_UART 6
+#define NPCM7XX_CLK_MMC 7
+#define NPCM7XX_CLK_SPI3 8
+#define NPCM7XX_CLK_PCI 9
+#define NPCM7XX_CLK_AXI 10
+#define NPCM7XX_CLK_APB4 11
+#define NPCM7XX_CLK_APB3 12
+#define NPCM7XX_CLK_APB2 13
+#define NPCM7XX_CLK_APB1 14
+#define NPCM7XX_CLK_APB5 15
+#define NPCM7XX_CLK_CLKOUT 16
+#define NPCM7XX_CLK_GFX 17
+#define NPCM7XX_CLK_SU 18
+#define NPCM7XX_CLK_SU48 19
+#define NPCM7XX_CLK_SDHC 20
+#define NPCM7XX_CLK_SPI0 21
+#define NPCM7XX_CLK_SPIX 22
+#define NPCM7XX_CLK_REFCLK 23
+#define NPCM7XX_CLK_SYSBYPCK 24
+#define NPCM7XX_CLK_MCBYPCK 25
+#define NPCM7XX_CLK_PLL0 26
+#define NPCM7XX_CLK_PLL1 27
+#define NPCM7XX_CLK_PLL2 28
+#define NPCM7XX_CLK_PLL2DIV2 29
+#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_PLL2DIV2 + 1)
+
+#endif
+