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authorwdenk <wdenk>2003-06-27 21:31:46 +0000
committerwdenk <wdenk>2003-06-27 21:31:46 +0000
commit8bde7f776c77b343aca29b8c7b58464d915ac245 (patch)
tree20f1fd99975215e7c658454a15cdb4ed4694e2d4 /include/dm9161.h
parent993cad9364c6b87ae429d1ed1130d8153f6f027e (diff)
* Code cleanup:LABEL_2003_06_27_2340
- remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
Diffstat (limited to 'include/dm9161.h')
-rw-r--r--include/dm9161.h64
1 files changed, 32 insertions, 32 deletions
diff --git a/include/dm9161.h b/include/dm9161.h
index 62999210a33..706e215af35 100644
--- a/include/dm9161.h
+++ b/include/dm9161.h
@@ -1,5 +1,5 @@
/*
- * NOTE: DAVICOM ethernet Physical layer
+ * NOTE: DAVICOM ethernet Physical layer
*
* Version: @(#)DM9161.h 1.0.0 01/10/2001
*
@@ -13,36 +13,36 @@
*/
-// DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161
-
-#define DM9161_BMCR 0 // Basic Mode Control Register
-#define DM9161_BMSR 1 // Basic Mode Status Register
-#define DM9161_PHYID1 2 // PHY Idendifier Register 1
-#define DM9161_PHYID2 3 // PHY Idendifier Register 2
-#define DM9161_ANAR 4 // Auto_Negotiation Advertisement Register
-#define DM9161_ANLPAR 5 // Auto_negotiation Link Partner Ability Register
-#define DM9161_ANER 6 // Auto-negotiation Expansion Register
-#define DM9161_DSCR 16 // Specified Configuration Register
-#define DM9161_DSCSR 17 // Specified Configuration and Status Register
-#define DM9161_10BTCSR 18 // 10BASE-T Configuration and Satus Register
-#define DM9161_MDINTR 21 // Specified Interrupt Register
-#define DM9161_RECR 22 // Specified Receive Error Counter Register
-#define DM9161_DISCR 23 // Specified Disconnect Counter Register
-#define DM9161_RLSR 24 // Hardware Reset Latch State Register
-
-
-// --Bit definitions: DM9161_BMCR
-#define DM9161_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
-#define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
-#define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
+/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
+
+#define DM9161_BMCR 0 /* Basic Mode Control Register */
+#define DM9161_BMSR 1 /* Basic Mode Status Register */
+#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */
+#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */
+#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */
+#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */
+#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */
+#define DM9161_DSCR 16 /* Specified Configuration Register */
+#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */
+#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */
+#define DM9161_MDINTR 21 /* Specified Interrupt Register */
+#define DM9161_RECR 22 /* Specified Receive Error Counter Register */
+#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */
+#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */
+
+
+/* --Bit definitions: DM9161_BMCR */
+#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
+#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
+#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
#define DM9161_AUTONEG (1 << 12)
#define DM9161_POWER_DOWN (1 << 11)
-#define DM9161_ISOLATE (1 << 10)
+#define DM9161_ISOLATE (1 << 10)
#define DM9161_RESTART_AUTONEG (1 << 9)
#define DM9161_DUPLEX_MODE (1 << 8)
#define DM9161_COLLISION_TEST (1 << 7)
-//--Bit definitions: DM9161_BMSR
+/*--Bit definitions: DM9161_BMSR */
#define DM9161_100BASE_T4 (1 << 15)
#define DM9161_100BASE_TX_FD (1 << 14)
#define DM9161_100BASE_T4_HD (1 << 13)
@@ -56,11 +56,11 @@
#define DM9161_JABBER_DETECT (1 << 1)
#define DM9161_EXTEND_CAPAB (1 << 0)
-//--definitions: DM9161_PHYID1
+/*--definitions: DM9161_PHYID1 */
#define DM9161_PHYID1_OUI 0x606E
#define DM9161_LSB_MASK 0x3F
-//--Bit definitions: DM9161_ANAR, DM9161_ANLPAR
+/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */
#define DM9161_NP (1 << 15)
#define DM9161_ACK (1 << 14)
#define DM9161_RF (1 << 13)
@@ -72,14 +72,14 @@
#define DM9161_10_HDX (1 << 5)
#define DM9161_AN_IEEE_802_3 0x0001
-//--Bit definitions: DM9161_ANER
+/*--Bit definitions: DM9161_ANER */
#define DM9161_PDF (1 << 4)
#define DM9161_LP_NP_ABLE (1 << 3)
#define DM9161_NP_ABLE (1 << 2)
#define DM9161_PAGE_RX (1 << 1)
#define DM9161_LP_AN_ABLE (1 << 0)
-//--Bit definitions: DM9161_DSCR
+/*--Bit definitions: DM9161_DSCR */
#define DM9161_BP4B5B (1 << 15)
#define DM9161_BP_SCR (1 << 14)
#define DM9161_BP_ALIGN (1 << 13)
@@ -96,13 +96,13 @@
#define DM9161_SLEEP (1 << 1)
#define DM9161_RLOUT (1 << 0)
-//--Bit definitions: DM9161_DSCSR
+/*--Bit definitions: DM9161_DSCSR */
#define DM9161_100FDX (1 << 15)
#define DM9161_100HDX (1 << 14)
#define DM9161_10FDX (1 << 13)
#define DM9161_10HDX (1 << 12)
-//--Bit definitions: DM9161_10BTCSR
+/*--Bit definitions: DM9161_10BTCSR */
#define DM9161_LP_EN (1 << 14)
#define DM9161_HBE (1 << 13)
#define DM9161_SQUELCH (1 << 12)
@@ -111,7 +111,7 @@
#define DM9161_POLR (1 << 0)
-//--Bit definitions: DM9161_MDINTR
+/*--Bit definitions: DM9161_MDINTR */
#define DM9161_INTR_PEND (1 << 15)
#define DM9161_FDX_MASK (1 << 11)
#define DM9161_SPD_MASK (1 << 10)