diff options
| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2009-10-07 15:47:48 -0400 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-10-07 15:47:48 -0400 |
| commit | 8ff56326996a13dd0755fbcd4f02694a074f2722 (patch) | |
| tree | a7dedb7c420ea757a5baf02386a77660b11ecb3b /include/configs | |
| parent | a8767736e48f5431e416aebbbb390e3d593fe259 (diff) | |
u-boot-2009.03-p2020rdb-RevB-DDR-changes
P2020RDB RevB changes mainly for DDR settings
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/P10XX_20XX_RDB.h | 82 |
1 files changed, 69 insertions, 13 deletions
diff --git a/include/configs/P10XX_20XX_RDB.h b/include/configs/P10XX_20XX_RDB.h index b4ef0064e8..8e2b6ea5b3 100644 --- a/include/configs/P10XX_20XX_RDB.h +++ b/include/configs/P10XX_20XX_RDB.h @@ -125,23 +125,79 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 /* Enable, no interleaving */ #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_TIMING_3 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x4c47a432 -#define CONFIG_SYS_DDR_TIMING_2 0x04984cce -#define CONFIG_SYS_DDR_TIMING_4 0x00000000 -#define CONFIG_SYS_DDR_TIMING_5 0x00000000 -#define CONFIG_SYS_DDR_MODE_1 0x00040642 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x08200100 + +#define CONFIG_SYS_DDR_TIMING_3_REVA 0x00010000 +#define CONFIG_SYS_DDR_TIMING_0_REVA 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1_REVA 0x4c47a432 +#define CONFIG_SYS_DDR_TIMING_2_REVA 0x04984cce +#define CONFIG_SYS_DDR_TIMING_4_REVA 0x00000000 +#define CONFIG_SYS_DDR_TIMING_5_REVA 0x00000000 +#define CONFIG_SYS_DDR_MODE_1_REVA 0x00040642 +#define CONFIG_SYS_DDR_MODE_2_REVA 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_REVA 0x08200100 +#define CONFIG_SYS_DDR_CLK_CTRL_REVA 0x03800000 +#define CONFIG_SYS_DDR_CONTROL_REVA 0x43000008 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL2_REVA 0x24400010 + +#define CONFIG_SYS_DDR_TIMING_3_533_REVB 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_533_REVB 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1_533_REVB 0x4c47c432 +#define CONFIG_SYS_DDR_TIMING_2_533_REVB 0x0f9848ce +#define CONFIG_SYS_DDR_TIMING_4_533_REVB 0x00000000 +#define CONFIG_SYS_DDR_TIMING_5_533_REVB 0x00000000 +#define CONFIG_SYS_DDR_CLK_CTRL_533_REVB 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_533_REVB 0x00040642 +#define CONFIG_SYS_DDR_MODE_2_533_REVB 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_533_REVB 0x08200100 +#define CONFIG_SYS_DDR_CONTROL_533_REVB 0x43000000 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL2_533_REVB 0x24401000 + + +#define CONFIG_SYS_DDR_TIMING_3_400_REVB 0x00010000 +#define CONFIG_SYS_DDR_TIMING_0_400_REVB 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1_400_REVB 0x39352322 +#define CONFIG_SYS_DDR_TIMING_2_400_REVB 0x1f9048ca +#define CONFIG_SYS_DDR_TIMING_4_400_REVB 0x00000000 +#define CONFIG_SYS_DDR_TIMING_5_400_REVB 0x00000000 +#define CONFIG_SYS_DDR_CLK_CTRL_400_REVB 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_400_REVB 0x00480432 +#define CONFIG_SYS_DDR_MODE_2_400_REVB 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_400_REVB 0x06180100 +#define CONFIG_SYS_DDR_CONTROL_400_REVB 0x43000000 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL2_400_REVB 0x24401000 + + +#define CONFIG_SYS_DDR_TIMING_3_667_REVB 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_667_REVB 0x55770802 +#define CONFIG_SYS_DDR_TIMING_1_667_REVB 0x5f599543 +#define CONFIG_SYS_DDR_TIMING_2_667_REVB 0x0fa074d1 +#define CONFIG_SYS_DDR_TIMING_4_667_REVB 0x00000000 +#define CONFIG_SYS_DDR_TIMING_5_667_REVB 0x00000000 +#define CONFIG_SYS_DDR_CLK_CTRL_667_REVB 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_667_REVB 0x00040852 +#define CONFIG_SYS_DDR_MODE_2_667_REVB 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_667_REVB 0x0a280100 +#define CONFIG_SYS_DDR_CONTROL_667_REVB 0x43000000 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL2_667_REVB 0x24401000 + +#define CONFIG_SYS_DDR_TIMING_3_800_REVB 0x00040000 +#define CONFIG_SYS_DDR_TIMING_0_800_REVB 0x55770802 +#define CONFIG_SYS_DDR_TIMING_1_800_REVB 0x6f6b6543 +#define CONFIG_SYS_DDR_TIMING_2_800_REVB 0x0fa074d1 +#define CONFIG_SYS_DDR_TIMING_4_800_REVB 0x00000000 +#define CONFIG_SYS_DDR_TIMING_5_800_REVB 0x00000000 +#define CONFIG_SYS_DDR_CLK_CTRL_800_REVB 0x02000000 +#define CONFIG_SYS_DDR_MODE_1_800_REVB 0x00440862 +#define CONFIG_SYS_DDR_MODE_2_800_REVB 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800_REVB 0x0a280100 +#define CONFIG_SYS_DDR_CONTROL_800_REVB 0x43000000 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL2_800_REVB 0x24401000 + + #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC3000008 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2 0x24400010 - #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 #define CONFIG_SYS_DDR_SBE 0x00FF0000 |