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authorwdenk <wdenk>2004-06-19 21:19:10 +0000
committerwdenk <wdenk>2004-06-19 21:19:10 +0000
commit49822e23a09e2f529e6774ad61f23e43ab208cbc (patch)
treed6cbe0c141f10778b944fddbfc473a91d4bea7c0 /include/configs
parent46a414dc12c7809ac3c3e82b6198a1f435d7489f (diff)
Patch by Josef Wagner, 04 Jun 2004:
- DDR Ram support for PM520 (MPC5200) - support for different flash types (PM520) - USB / IDE / CF-Card / DiskOnChip support for PM520 - 8 bit boot rom support for PM520/CE520 - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) - I2C and RTC support for CPC45 - support of new flash type (28F160C3T) for CPC45
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/CPC45.h404
-rw-r--r--include/configs/PM520.h154
-rw-r--r--include/configs/RPXlite_DW.h2
-rw-r--r--include/configs/Sandpoint8245.h2
-rw-r--r--include/configs/mx1ads.h24
5 files changed, 370 insertions, 216 deletions
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index 66f978ebc2..5a00133775 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -59,10 +59,13 @@
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_DATE | \
CFG_CMD_DHCP | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
CFG_CMD_PCI | \
- 0 /* CFG_CMD_DATE */ )
+ CFG_CMD_SDRAM )
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
*/
@@ -77,17 +80,17 @@
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#if 1
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#endif
#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* Print Buffer Size
*/
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
-#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
@@ -97,29 +100,29 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE 0x00000000
#if defined(CONFIG_BOOT_ROM)
-#define CFG_FLASH_BASE 0xFF000000
+#define CFG_FLASH_BASE 0xFF000000
#else
-#define CFG_FLASH_BASE 0xFF800000
+#define CFG_FLASH_BASE 0xFF800000
#endif
-#define CFG_RESET_ADDRESS 0xFFF00100
+#define CFG_RESET_ADDRESS 0xFFF00100
-#define CFG_EUMB_ADDR 0xFCE00000
+#define CFG_EUMB_ADDR 0xFCE00000
-#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
-#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
+#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
+#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
- /* Maximum amount of RAM.
- */
-#define CFG_MAX_RAM_SIZE 0x10000000
+/* Maximum amount of RAM.
+ */
+#define CFG_MAX_RAM_SIZE 0x10000000
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
@@ -133,13 +136,13 @@
* Definitions for initial stack pointer and data area
*/
- /* Size in bytes reserved for initial data
- */
-#define CFG_GBL_DATA_SIZE 128
+/* Size in bytes reserved for initial data
+ */
+#define CFG_GBL_DATA_SIZE 128
-#define CFG_INIT_RAM_ADDR 0x40000000
-#define CFG_INIT_RAM_END 0x1000
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
* NS16550 Configuration
@@ -153,7 +156,30 @@
#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
-#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
+#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR 0x51
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR 0x58
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
/*
* Low Level Configuration Settings
@@ -162,62 +188,49 @@
* For the detail description refer to the MPC8240 user's manual.
*/
-#define CONFIG_SYS_CLK_FREQ 33000000
-#define CFG_HZ 1000
-/*
- * SDRAM Configuration Settings
- * Please note: currently only 64 and 128 MB SDRAM size supported
- * set CFG_SDRAM_SIZE to 64 or 128
- * Memory configuration using SPD information stored on the SODIMMs
- * not yet supported.
- */
+#define CONFIG_SYS_CLK_FREQ 33000000
+#define CFG_HZ 1000
-#define CFG_SDRAM_SIZE 64 /* SDRAM size -- 64 or 128 MB supported */
- /* Bit-field values for MCCR1.
- */
-#define CFG_ROMNAL 0
-#define CFG_ROMFAL 7
+/* Bit-field values for MCCR1.
+ */
+#define CFG_ROMNAL 0
+#define CFG_ROMFAL 8
+
+#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
+#define CFG_BANK1_ROW 0
+#define CFG_BANK2_ROW 0
+#define CFG_BANK3_ROW 0
+#define CFG_BANK4_ROW 0
+#define CFG_BANK5_ROW 0
+#define CFG_BANK6_ROW 0
+#define CFG_BANK7_ROW 0
+
+/* Bit-field values for MCCR2.
+ */
-#if (CFG_SDRAM_SIZE == 64) /* 64 MB */
-#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
-#elif (CFG_SDRAM_SIZE == 128) /* 128 MB */
-#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */
-#else
-# error "SDRAM size not supported"
-#endif
-#define CFG_BANK1_ROW 0
-#define CFG_BANK2_ROW 0
-#define CFG_BANK3_ROW 0
-#define CFG_BANK4_ROW 0
-#define CFG_BANK5_ROW 0
-#define CFG_BANK6_ROW 0
-#define CFG_BANK7_ROW 0
-
- /* Bit-field values for MCCR2.
- */
-#define CFG_REFINT 430 /* Refresh interval */
+#define CFG_REFINT 0x2ec
- /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
- */
-#define CFG_BSTOPRE 192
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+ */
+#define CFG_BSTOPRE 160
- /* Bit-field values for MCCR3.
- */
-#define CFG_REFREC 2 /* Refresh to activate interval */
-#define CFG_RDLAT 3 /* Data latancy from read command */
+/* Bit-field values for MCCR3.
+ */
+#define CFG_REFREC 2 /* Refresh to activate interval */
+#define CFG_RDLAT 0 /* Data latancy from read command */
- /* Bit-field values for MCCR4.
- */
-#define CFG_PRETOACT 2 /* Precharge to activate interval */
-#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
-#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
-#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
-#define CFG_ACTORW 2
+/* Bit-field values for MCCR4.
+ */
+#define CFG_PRETOACT 2 /* Precharge to activate interval */
+#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
+#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
+#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
+#define CFG_ACTORW 2
#define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM 1
-#define CFG_REGDIMM 0
+#define CFG_EXTROM 0
+#define CFG_REGDIMM 0
/* Memory bank settings.
* Only bits 20-29 are actually used from these vales to set the
@@ -226,32 +239,35 @@
* address. Refer to the MPC8240 book.
*/
-#define CFG_BANK0_START 0x00000000
-#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE 1
-#define CFG_BANK1_START 0x3ff00000
-#define CFG_BANK1_END 0x3fffffff
-#define CFG_BANK1_ENABLE 0
-#define CFG_BANK2_START 0x3ff00000
-#define CFG_BANK2_END 0x3fffffff
-#define CFG_BANK2_ENABLE 0
-#define CFG_BANK3_START 0x3ff00000
-#define CFG_BANK3_END 0x3fffffff
-#define CFG_BANK3_ENABLE 0
-#define CFG_BANK4_START 0x3ff00000
-#define CFG_BANK4_END 0x3fffffff
-#define CFG_BANK4_ENABLE 0
-#define CFG_BANK5_START 0x3ff00000
-#define CFG_BANK5_END 0x3fffffff
-#define CFG_BANK5_ENABLE 0
-#define CFG_BANK6_START 0x3ff00000
-#define CFG_BANK6_END 0x3fffffff
-#define CFG_BANK6_ENABLE 0
-#define CFG_BANK7_START 0x3ff00000
-#define CFG_BANK7_END 0x3fffffff
-#define CFG_BANK7_ENABLE 0
-
-#define CFG_ODCR 0xff
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START 0x3ff00000
+#define CFG_BANK1_END 0x3fffffff
+#define CFG_BANK1_ENABLE 0
+#define CFG_BANK2_START 0x3ff00000
+#define CFG_BANK2_END 0x3fffffff
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x3ff00000
+#define CFG_BANK3_END 0x3fffffff
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x3ff00000
+#define CFG_BANK4_END 0x3fffffff
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x3ff00000
+#define CFG_BANK5_END 0x3fffffff
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x3ff00000
+#define CFG_BANK6_END 0x3fffffff
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x3ff00000
+#define CFG_BANK7_END 0x3fffffff
+#define CFG_BANK7_ENABLE 0
+
+#define CFG_ODCR 0xff
+#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
+ /* currently accessed page in memory */
+ /* see 8240 book for details */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@@ -279,7 +295,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
@@ -295,7 +311,7 @@
*/
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7C0000)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7F8000)
#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
@@ -317,118 +333,118 @@
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define SRAM_BASE 0x80000000 /* SRAM base address */
-#define SRAM_END 0x801FFFFF
+#define SRAM_BASE 0x80000000 /* SRAM base address */
+#define SRAM_END 0x801FFFFF
-/*---------------------------------------------------------------------*/
-/* CPC45 Memory Map */
-/*---------------------------------------------------------------------*/
-#define SRAM_BASE 0x80000000 /* SRAM base address */
-#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
-#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
-#define BCSR_BASE 0x80600000 /* board control / status registers */
-#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
-#define PCMCIA_MEM_BASE 0x81000000 /* PCMCIA memory window base */
-#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
+/*----------------------------------------------------------------------*/
+/* CPC45 Memory Map */
+/*----------------------------------------------------------------------*/
+#define SRAM_BASE 0x80000000 /* SRAM base address */
+#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
+#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
+#define BCSR_BASE 0x80600000 /* board control / status registers */
+#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
+#define PCMCIA_MEM_BASE 0x81000000 /* PCMCIA memory window base */
+#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
/*---------------------------------------------------------------------*/
-/* CPC45 Control/Status Registers */
+/* CPC45 Control/Status Registers */
/*---------------------------------------------------------------------*/
-#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
-#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
-#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
-#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
-#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
-#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
-#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
-#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
-#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
-#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
+#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
+#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
+#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
+#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
+#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
+#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
+#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
+#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
/* IRQ_ENA_1 bit definitions */
-#define I_ENA_1_IERA 0x80 /* INTA enable */
-#define I_ENA_1_IERB 0x40 /* INTB enable */
-#define I_ENA_1_IERC 0x20 /* INTC enable */
-#define I_ENA_1_IERD 0x10 /* INTD enable */
+#define I_ENA_1_IERA 0x80 /* INTA enable */
+#define I_ENA_1_IERB 0x40 /* INTB enable */
+#define I_ENA_1_IERC 0x20 /* INTC enable */
+#define I_ENA_1_IERD 0x10 /* INTD enable */
/* IRQ_STAT_1 bit definitions */
-#define I_STAT_1_INTA 0x80 /* INTA status */
-#define I_STAT_1_INTB 0x40 /* INTB status */
-#define I_STAT_1_INTC 0x20 /* INTC status */
-#define I_STAT_1_INTD 0x10 /* INTD status */
+#define I_STAT_1_INTA 0x80 /* INTA status */
+#define I_STAT_1_INTB 0x40 /* INTB status */
+#define I_STAT_1_INTC 0x20 /* INTC status */
+#define I_STAT_1_INTD 0x10 /* INTD status */
/* IRQ_ENA_2 bit definitions */
-#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
-#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
-#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
-#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
-#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
-#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
-#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
-#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
+#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
+#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
+#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
+#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
+#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
+#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
+#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
+#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
/* IRQ_STAT_2 bit definitions */
-#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
-#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
-#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
-#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
-#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
-#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
-#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
-#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
+#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
+#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
+#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
+#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
+#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
+#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
+#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
+#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
/* BOARD_CTRL bit definitions */
-#define USER_LEDS 2 /* 2 user LEDs */
+#define USER_LEDS 2 /* 2 user LEDs */
#if (USER_LEDS == 4)
-#define B_CTRL_WRSE 0x80
-#define B_CTRL_KRSE 0x40
-#define B_CTRL_FWRE 0x20 /* Flash write enable */
-#define B_CTRL_FWPT 0x10 /* Flash write protect */
-#define B_CTRL_LED3 0x08 /* LED 3 control */
-#define B_CTRL_LED2 0x04 /* LED 2 control */
-#define B_CTRL_LED1 0x02 /* LED 1 control */
-#define B_CTRL_LED0 0x01 /* LED 0 control */
+#define B_CTRL_WRSE 0x80
+#define B_CTRL_KRSE 0x40
+#define B_CTRL_FWRE 0x20 /* Flash write enable */
+#define B_CTRL_FWPT 0x10 /* Flash write protect */
+#define B_CTRL_LED3 0x08 /* LED 3 control */
+#define B_CTRL_LED2 0x04 /* LED 2 control */
+#define B_CTRL_LED1 0x02 /* LED 1 control */
+#define B_CTRL_LED0 0x01 /* LED 0 control */
#else
-#define B_CTRL_WRSE 0x80
-#define B_CTRL_KRSE 0x40
-#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
-#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
-#define B_CTRL_LED1 0x08 /* LED 1 control */
-#define B_CTRL_LED0 0x04 /* LED 0 control */
-#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
-#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
+#define B_CTRL_WRSE 0x80
+#define B_CTRL_KRSE 0x40
+#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
+#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
+#define B_CTRL_LED1 0x08 /* LED 1 control */
+#define B_CTRL_LED0 0x04 /* LED 0 control */
+#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
+#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
#endif
/* BOARD_STAT bit definitions */
-#define B_STAT_WDGE 0x80
-#define B_STAT_WDGS 0x40
-#define B_STAT_WRST 0x20
-#define B_STAT_KRST 0x10
-#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
-#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
-#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
-#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
+#define B_STAT_WDGE 0x80
+#define B_STAT_WDGS 0x40
+#define B_STAT_WRST 0x20
+#define B_STAT_KRST 0x10
+#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
+#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
+#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
+#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
/*---------------------------------------------------------------------*/
-/* Display addresses */
+/* Display addresses */
/*---------------------------------------------------------------------*/
-#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
-#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
-#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
+#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
+#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
+#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
-#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
-#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
+#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
+#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
-#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
-#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
-#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
-#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
-#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
-#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
-#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
-#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
+#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
+#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
+#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
+#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
+#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
+#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
+#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
+#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
/*-----------------------------------------------------------------------
@@ -436,14 +452,16 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP
+#undef CONFIG_PCI_PNP
+#undef CONFIG_PCI_SCAN_SHOW
-#define CONFIG_NET_MULTI /* Multi ethernet cards support */
+#define CONFIG_NET_MULTI /* Multi ethernet cards support */
#define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define PCI_ENET0_IOADDR 0x00104000
+#define PCI_ENET0_IOADDR 0x82000000
#define PCI_ENET0_MEMADDR 0x82000000
-#define PCI_PLX9030_MEMADDR 0x82100000
+#define PCI_PLX9030_IOADDR 0x82100000
+#define PCI_PLX9030_MEMADDR 0x82100000
#endif /* __CONFIG_H */
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index a7d30f0d75..a91662cf95 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -35,6 +35,8 @@
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
+#define CONFIG_MISC_INIT_R
+
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
@@ -82,11 +84,37 @@
#endif
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 1
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD 0
+#endif
+
+#if defined(CONFIG_BOOT_ROM)
+#define ADD_DOC_CMD 0
+#else
+#define ADD_DOC_CMD CFG_CMD_DOC
+#endif
+
/*
* Supported commands
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
- CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_DATE)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ ADD_DOC_CMD | \
+ ADD_PCI_CMD | \
+ CFG_CMD_DATE | \
+ CFG_CMD_BEDBUG | \
+ ADD_USB_CMD)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -95,8 +123,32 @@
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=pm520\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk30/ppc_82xx\0" \
+ "bootfile=/tftpboot/PM520/uImage\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
#if defined(CONFIG_MPC5200)
/*
@@ -128,11 +180,44 @@
#define CFG_I2C_RTC_ADDR 0x51
/*
- * Flash configuration
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
+
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CFG_DOC_BASE 0xE0000000
+#define CFG_DOC_SIZE 0x00100000
+
+#if defined(CONFIG_BOOT_ROM)
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at 0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 32 MB
+ * 0xFD000000 for 16 MB
+ * 0xFD800000 for 8 MB
+ */
+#define CFG_FLASH_BASE 0xfc000000
+#define CFG_FLASH_SIZE 0x02000000
+#define CFG_BOOTROM_BASE 0xFFF00000
+#define CFG_BOOTROM_SIZE 0x00080000
+#define CFG_ENV_ADDR (0xFDF00000 + 0x40000)
+#else
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at 0xFFF40000
+ * FLASH_BASE at 0xFE000000 for 32 MB
+ * 0xFF000000 for 16 MB
+ * 0xFF800000 for 8 MB
*/
-#define CFG_FLASH_BASE 0xff800000
-#define CFG_FLASH_SIZE 0x00800000
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
+#define CFG_FLASH_BASE 0xfe000000
+#define CFG_FLASH_SIZE 0x02000000
+#define CFG_ENV_ADDR (0xFFF00000 + 0x40000)
+#endif
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
@@ -228,15 +313,68 @@
#define CFG_HID0_FINAL 0
#endif
+#if defined(CONFIG_BOOT_ROM)
+#define CFG_BOOTCS_START CFG_BOOTROM_BASE
+#define CFG_BOOTCS_SIZE CFG_BOOTROM_SIZE
+#define CFG_BOOTCS_CFG 0x00047800
+#define CFG_CS0_START CFG_BOOTROM_BASE
+#define CFG_CS0_SIZE CFG_BOOTROM_SIZE
+#define CFG_CS1_START CFG_FLASH_BASE
+#define CFG_CS1_SIZE CFG_FLASH_SIZE
+#define CFG_CS1_CFG 0x0004fb00
+#else
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG 0x0004fb00
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
+#define CFG_CS1_START CFG_DOC_BASE
+#define CFG_CS1_SIZE CFG_DOC_SIZE
+#define CFG_CS1_CFG 0x00047800
+#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CFG_RESET_ADDRESS 0xff000000
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00005000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#undef CONFIG_IDE_RESET /* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
+
#endif /* __CONFIG_H */
diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h
index ff63259b5c..369842b13a 100644
--- a/include/configs/RPXlite_DW.h
+++ b/include/configs/RPXlite_DW.h
@@ -178,8 +178,6 @@
#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
#endif
-
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index 9611d61032..46c6fdd697 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -229,7 +229,7 @@
#else
#define CFG_NS16550_CLK 1843200
#endif
-
+
#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500)
diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
index 9d4ab2b52e..5cf092af55 100644
--- a/include/configs/mx1ads.h
+++ b/include/configs/mx1ads.h
@@ -1,6 +1,6 @@
/*
* include/configs/mx1ads.h
- *
+ *
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@@ -43,17 +43,17 @@
#define CONFIG_MC9328 1 /* It's a Motorola MC9328 SoC */
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
-#define BOARD_LATE_INIT 1
+#define BOARD_LATE_INIT 1
#define USE_920T_MMU 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-#if 0
+#if 0
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
-#endif
+#endif
/*
* Size of malloc() pool
@@ -73,7 +73,7 @@
* select serial console configuration
*/
-#define CONFIG_UART1 1
+#define CONFIG_UART1 1
/* #define CONFIG_UART2 1 */
#define CONFIG_BAUDRATE 115200
@@ -90,13 +90,13 @@
/*CFG_CMD_I2C |*/ \
/*CFG_CMD_USB |*/ \
CFG_CMD_REGINFO | \
- CFG_CMD_ELF)
+ CFG_CMD_ELF)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M"
+#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5c
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.22
@@ -113,10 +113,10 @@
/*
* Miscellaneous configurable options
*/
-
+
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-
+
#define CFG_LONGHELP /* undef to save memory */
#ifdef CFG_HUSH_PARSER
@@ -126,7 +126,7 @@
#endif
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
/* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@@ -158,7 +158,7 @@
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-
+
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
@@ -178,7 +178,7 @@
#define PHYS_FLASH_SIZE 0x01000000
#define CFG_MAX_FLASH_SECT (16)
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff0000)
-
+
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x0f000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x100000