Merge branch 'master' of git://www.denx.de/git/u-boot-at91

6 files changed, 211 insertions, 49 deletions

diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index f0dfd71aef..dab21d0c0a 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stelian Pop <stelian.pop <at> leadtechdesign.com>
  * Lead Tech Design <www.leadtechdesign.com>
  *
@@ -28,8 +28,8 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91C_MAIN_CLOCK	200000000	/* from 12 MHz crystal */
-#define AT91C_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
+#define AT91_MAIN_CLOCK		200000000	/* from 12 MHz crystal */
+#define AT91_MASTER_CLOCK	100000000	/* peripheral = main / 2 */
 #define CFG_HZ			1000000		/* 1us resolution */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
@@ -46,19 +46,9 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SKIP_RELOCATE_UBOOT
 
-#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
-/*
- * Size of malloc() pool
- */
-#define CFG_MALLOC_LEN		ROUND(CFG_ENV_SIZE + 128*1024, 0x1000)
-#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
-
-#define CONFIG_BAUDRATE		115200
-
 /*
  * Hardware drivers
  */
-
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
@@ -104,7 +94,9 @@
 #define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
 #define CFG_MAX_DATAFLASH_BANKS		1
 #define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
-#define CONFIG_NEW_PARTITION		1
+#define AT91_SPI_CLK			20000000
+#define DATAFLASH_TCSS			(0xFA << 16)
+#define DATAFLASH_TCHS			(0x8 << 24)
 
 /* NOR flash */
 #define CFG_FLASH_CFI			1
@@ -114,39 +106,11 @@
 #define CFG_MAX_FLASH_SECT		256
 #define CFG_MAX_FLASH_BANKS		1
 
-#define AT91C_FLASH_NWE_SETUP		(4 << 0)
-#define AT91C_FLASH_NCS_WR_SETUP	(2 << 8)
-#define AT91C_FLASH_NRD_SETUP		(4 << 16)
-#define AT91C_FLASH_NCS_RD_SETUP	(2 << 24)
-
-#define AT91C_FLASH_NWE_PULSE		(8 << 0)
-#define AT91C_FLASH_NCS_WR_PULSE	(10 << 8)
-#define AT91C_FLASH_NRD_PULSE		(8 << 16)
-#define AT91C_FLASH_NCS_RD_PULSE	(10 << 24)
-
-#define AT91C_FLASH_NWE_CYCLE		(16 << 0)
-#define AT91C_FLASH_NRD_CYCLE		(16 << 16)
-
 /* NAND flash */
 #define NAND_MAX_CHIPS			1
 #define CFG_MAX_NAND_DEVICE		1
 #define CFG_NAND_BASE			0x40000000
 
-#define AT91C_SM_NWE_SETUP		(2 << 0)
-#define AT91C_SM_NCS_WR_SETUP		(1 << 8)
-#define AT91C_SM_NRD_SETUP		(2 << 16)
-#define AT91C_SM_NCS_RD_SETUP		(1 << 24)
-
-#define AT91C_SM_NWE_PULSE		(4 << 0)
-#define AT91C_SM_NCS_WR_PULSE		(6 << 8)
-#define AT91C_SM_NRD_PULSE		(4 << 16)
-#define AT91C_SM_NCS_RD_PULSE		(6 << 24)
-
-#define AT91C_SM_NWE_CYCLE		(8 << 0)
-#define AT91C_SM_NRD_CYCLE		(8 << 16)
-
-#define AT91C_SM_TDF			(1 << 16)
-
 /* Ethernet */
 #define CONFIG_MACB			1
 #define CONFIG_RMII			1
@@ -159,15 +123,14 @@
 #define LITTLEENDIAN			1
 #define CONFIG_DOS_PARTITION		1
 #define CFG_USB_OHCI_CPU_INIT		1
-#define CFG_USB_OHCI_REGS_BASE		0x00700000	/* AT91C_BASE_UHP */
+#define CFG_USB_OHCI_REGS_BASE		0x00700000	/* AT91_BASE_UHP */
 #define CFG_USB_OHCI_SLOT_NAME		"at91cap9"
 #define CFG_USB_OHCI_MAX_ROOT_PORTS	2
 
-
 #define CFG_LOAD_ADDR			0x72000000	/* load address */
 
 #define CFG_MEMTEST_START		PHYS_SDRAM
-#define CFG_MEMTEST_END			0x73000000
+#define CFG_MEMTEST_END			0x73e00000
 
 #define CFG_USE_DATAFLASH		1
 #undef CFG_USE_NORFLASH
@@ -194,6 +157,7 @@
 
 #endif
 
+#define CONFIG_BAUDRATE		115200
 #define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
 #define CFG_PROMPT		"U-Boot> "
@@ -203,6 +167,13 @@
 #define CFG_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
+#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		ROUND(CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
 #ifdef CONFIG_USE_IRQ
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 5b7212a68f..951ce160a4 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -51,7 +51,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
new file mode 100644
index 0000000000..96d1b8dff3
--- /dev/null
+++ b/include/configs/at91sam9260ek.h
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9260EK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK		198656000	/* from 18.432 MHz crystal */
+#define AT91_MASTER_CLOCK	99328000	/* peripheral = main / 2 */
+#define CFG_HZ			1000000		/* 1us resolution */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
+#define CONFIG_AT91SAM9260	1	/* It's an Atmel AT91SAM9260 SoC*/
+#define CONFIG_AT91SAM9260EK	1	/* on an AT91SAM9260EK Board	*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART	1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3		1	/* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock0 rw rootfstype=jffs2"
+
+/* #define CONFIG_ENV_OVERWRITE	1 */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_USB		1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x20000000
+#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH		1
+#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS		2
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CFG_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */
+#define AT91_SPI_CLK			33000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+/* NAND flash */
+#define NAND_MAX_CHIPS			1
+#define CFG_MAX_NAND_DEVICE		1
+#define CFG_NAND_BASE			0x40000000
+
+/* NOR flash - no real flash on this board */
+#define CFG_NO_FLASH			1
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#define CONFIG_RMII			1
+#define CONFIG_NET_MULTI		1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW		1
+#define LITTLEENDIAN			1
+#define CONFIG_DOS_PARTITION		1
+#define CFG_USB_OHCI_CPU_INIT		1
+#define CFG_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
+#define CFG_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE		1
+
+#define CFG_LOAD_ADDR			0x22000000	/* load address */
+
+#define CFG_MEMTEST_START		PHYS_SDRAM
+#define CFG_MEMTEST_END			0x23e00000
+
+#undef CFG_USE_DATAFLASH_CS0
+#define CFG_USE_DATAFLASH_CS1		1
+#undef CFG_USE_NANDFLASH
+
+#ifdef CFG_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CFG_ENV_IS_IN_DATAFLASH	1
+#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET		0x4200
+#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC003DE00 0x22000000 0x200040; bootm"
+
+#elif CFG_USE_DATAFLASH_CS1
+
+/* bootstrap + u-boot + env + linux in dataflash on CS1 */
+#define CFG_ENV_IS_IN_DATAFLASH	1
+#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
+#define CFG_ENV_OFFSET		0x4200
+#define CFG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xD003DE00 0x22000000 0x200040; bootm"
+
+#else /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x60000
+#define CFG_ENV_OFFSET_REDUND	0x80000
+#define CFG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT		"U-Boot> "
+#define CFG_CBSIZE		256
+#define CFG_MAXARGS		16
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+
+#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index d22d350579..bce5fcd82f 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -50,7 +50,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index f93c3bcd6f..e9c6d8e7ae 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -51,7 +51,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x2031BE01 /* 184.320000 MHz for PCK */
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 294221f941..2eb4af1554 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -55,7 +55,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x20263E04 /* 180 MHz for PCK */