* Patches by Xianghua Xiao, 15 Oct 2003:LABEL_2003_10_16_0200

  - Added Motorola CPU 8540/8560 support (cpu/85xx)
  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
  - Added Motorola MPC8560ADS board support (board/mpc8560ads)

* Minor code cleanup

11 files changed, 807 insertions, 103 deletions

diff --git a/include/configs/AdderII.h b/include/configs/AdderII.h
index 4c2ba7d582a..5e0bbe36f5b 100644
--- a/include/configs/AdderII.h
+++ b/include/configs/AdderII.h
@@ -146,7 +146,6 @@
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
-
 /* SIU Module Configuration Register */
 #define CFG_SIUMCR		( SIUMCR_AEME | SIUMCR_MLRC01 | SIUMCR_DBGC10 )
 
@@ -171,7 +170,7 @@
 
 /* PLPRCR - PLL, Low-Power, and Reset Control Register */
 #define CFG_PLPRCR      	((( MPC8XX_FACT - 1 ) << PLPRCR_MF_SHIFT ) | \
-                                PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST )
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST )
 
 /* SCCR - System Clock and reset Control Register */
 #define SCCR_MASK       	SCCR_EBDF11
@@ -223,4 +222,3 @@
 
 #endif
 /* __CONFIG_H */
-
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
new file mode 100644
index 00000000000..951d1fefb09
--- /dev/null
+++ b/include/configs/MPC8540ADS.h
@@ -0,0 +1,331 @@
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8540ads board configuration file */
+/* please refer to doc/README.mpc85xxads for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	    /* BOOKE 			*/
+#define CONFIG_E500		1	    /* BOOKE e500 family	*/
+#define CONFIG_MPC85xx		1	    /* MPC8540/MPC8560		*/
+#define CONFIG_MPC85xx_REV1	1	    /* MPC85xx Rev 1 Chip       */
+#define CONFIG_MPC8540		1	    /* MPC8540 specific	        */
+#define CONFIG_MPC8540ADS	1	    /* MPC8540ADS board specific*/
+
+#undef  CONFIG_PCI	         	    /* pci ethernet support	*/
+#define CONFIG_TSEC_ENET 		    /* tsec ethernet support  */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+
+#if defined(CONFIG_MPC85xx_REV1)
+#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+#endif
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+#if !defined(CONFIG_PCI) 		    /* some PCI card is 33Mhz only */
+#define CONFIG_SYS_CLK_FREQ	66000000    /* sysclk for MPC85xx	*/
+#else
+#define CONFIG_SYS_CLK_FREQ	33000000    /* most pci cards are 33Mhz */
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)             /* manually set up DDR parameters */
+#define CONFIG_DDR_SETTING
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#undef  CONFIG_BTB			    /* toggle branch predition */
+#undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+
+#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
+
+#undef	CFG_DRAM_TEST			    /* memory test, takes time  */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00400000
+
+#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
+#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR 	*/
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE		128             /* DDR is now 128MB     */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
+#else
+#define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
+#endif
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_FLASH_BASE    	0xf8000000	/* start of FLASH  16M	*/
+#define CFG_BR0_PRELIM		0xf8001801	/* port size 32bit */
+#else /* Boot from real Flash */
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M    */
+#define CFG_BR0_PRELIM		0xff001801	/* port size 32bit	*/
+#endif
+
+#define	CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash		*/
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+#if defined(CONFIG_DDR_SETTING)
+#define CFG_DDR_CS0_BNDS        0x00000007      /* 0-128MB              */
+#define CFG_DDR_CS0_CONFIG      0x80000002
+#define CFG_DDR_TIMING_1        0x37344321
+#define CFG_DDR_TIMING_2        0x00000800      /* P9-45,may need tuning*/
+#define CFG_DDR_CONTROL         0xc2000000      /* unbuffered,no DYN_PWR*/
+#define CFG_DDR_MODE            0x00000062      /* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL        0x05200100      /* autocharge,no open page*/
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CFG_OR2_PRELIM		0xfc006901
+#define CFG_LBC_LCRR		0x00030004	/* local bus freq divider*/
+#define CFG_LBC_LBCR		0x00000000
+#define CFG_LBC_LSRT		0x20000000
+#define CFG_LBC_MRTPR		0x20000000
+#define CFG_LBC_LSDMR_1		0x2861b723
+#define CFG_LBC_LSDMR_2		0x0861b723
+#define CFG_LBC_LSDMR_3		0x0861b723
+#define CFG_LBC_LSDMR_4		0x1861b723
+#define CFG_LBC_LSDMR_5		0x4061b723
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#else
+#define CFG_BR4_PRELIM          0xfc000801      /* 32KB, 8-bit wide for ADS config reg */
+#endif
+#define CFG_OR4_PRELIM          0xffffe1f1
+#define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR   	0x40000000 	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_BAUDRATE	 	115200
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/* General PCI */
+#define CFG_PCI_MEM_BASE	0xe0000000
+#define CFG_PCI_MEM_PHYS	0xe0000000
+#define CFG_PCI_MEM_SIZE	0x10000000
+#if defined(CONFIG_PCI)
+#define CONFIG_NET_MULTI
+#undef CONFIG_EEPRO100
+#define CONFIG_TULIP
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+  #if !defined(CONFIG_PCI_PNP)
+  #define PCI_ENET0_IOADDR      0xe0000000
+  #define PCI_ENET0_MEMADDR     0xe0000000
+  #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+  #endif
+#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#if defined(CONFIG_MPC85xx_REV1)	/* Errata PCI 8 */
+  #define CFG_PCI_SUBSYS_DEVICEID 0x0003
+#else
+  #define CFG_PCI_SUBSYS_DEVICEID 0x0008
+#endif
+#elif defined(CONFIG_TSEC_ENET)
+#define CONFIG_NET_MULTI 	1
+#define CONFIG_PHY_M88E1011      1       /* GigaBit Ether PHY    */
+#define CONFIG_MII		1	/* MII PHY management	*/
+#define CONFIG_PHY_ADDR		8	/* PHY address	*/
+#endif
+
+/* Environment */
+#ifndef CFG_RAMBOOT
+  #if defined(CONFIG_RAM_AS_FLASH)
+  #define CFG_ENV_IS_NOWHERE
+  #define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
+  #define CFG_ENV_SIZE		0x2000
+  #else
+  #define CFG_ENV_IS_IN_FLASH	1
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #endif
+  #define CFG_ENV_SIZE		0x2000
+#else
+#define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_BOOTARGS	"root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200"
+/*#define CONFIG_BOOTARGS	"root=/dev/ram rw console=ttyS0,115200"*/
+#define CONFIG_BOOTCOMMAND	"bootm 0xff300000 0xff700000"
+#define CONFIG_BOOTDELAY	3 	/* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+  #if defined(CONFIG_PCI)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_PCI | CFG_CMD_I2C ) & \
+				 ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
+  #else
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) & \
+				 ~(CFG_CMD_ENV | \
+				  CFG_CMD_LOADS ))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_PING | CFG_CMD_I2C )
+  #else
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
+  #endif
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"MPC8540ADS=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x1000000	/* default load address */
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/* NOTE: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR  00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
+#endif
+
+#define CONFIG_SERVERIP         163.12.64.52
+#define CONFIG_IPADDR           10.82.0.105
+#define CONFIG_GATEWAYIP        10.82.1.254
+#define CONFIG_NETMASK          255.255.254.0
+#define CONFIG_HOSTNAME         MPC8560ADS_PILOT_003
+#define CONFIG_ROOTPATH         /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
+#define CONFIG_BOOTFILE         pImage
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
new file mode 100644
index 00000000000..0d844d1c0b8
--- /dev/null
+++ b/include/configs/MPC8560ADS.h
@@ -0,0 +1,377 @@
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE		*/
+#define CONFIG_E500		1	/* BOOKE e500 family	*/
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
+#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip */
+#define CONFIG_MPC8560		1	/* MPC8560 specific	*/
+#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific*/
+
+#undef  CONFIG_PCI	         	/* pci ethernet support	*/
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support*/
+#undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
+
+#if defined(CONFIG_MPC85xx_REV1)
+#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
+#endif
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you need a flash-boot image(u-boot.bin), if so undef this.
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+#if !defined(CONFIG_PCI)		/* some PCI card is 33Mhz only */
+#define CONFIG_SYS_CLK_FREQ	66000000/* sysclk for MPC85xx */
+#else
+#define CONFIG_SYS_CLK_FREQ     33000000/* most pci cards are 33Mhz */
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)		/* manually set up DDR parameters */
+#define CONFIG_DDR_SETTING
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE                     /* toggle L2 cache         */
+#undef  CONFIG_BTB                          /* toggle branch predition */
+#undef  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
+
+#define CONFIG_BOARD_PRE_INIT   1           /* Call board_pre_init      */
+
+#undef  CFG_DRAM_TEST                       /* memory test, takes time  */
+#define CFG_MEMTEST_START       0x00200000  /* memtest region */
+#define CFG_MEMTEST_END         0x00400000
+
+#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
+     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
+     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
+#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE		128		/* DDR is 128MB	*/
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_LBC_SDRAM_BASE      0xfc000000      /* Localbus SDRAM */
+#else
+#define CFG_LBC_SDRAM_BASE      0xf8000000      /* Localbus SDRAM */
+#endif
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_FLASH_BASE        0xf8000000      /* start of FLASH  16M  */
+#define CFG_BR0_PRELIM        0xf8001801      /* port size 32bit */
+#else /* Boot from real Flash */
+#define CFG_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
+#define CFG_BR0_PRELIM        0xff001801      /* port size 32bit      */
+#endif
+
+#define CFG_OR0_PRELIM          0xff006ff7      /* 16MB Flash           */
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor	*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define SPD_EEPROM_ADDRESS 	0x51     	/*  DDR DIMM */
+
+#if defined(CONFIG_DDR_SETTING)
+#define	CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CFG_DDR_CS0_CONFIG	0x80000002
+#define CFG_DDR_TIMING_1	0x37344321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning*/
+#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR*/
+#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page*/
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CFG_OR2_PRELIM		0xfc006901
+#define CFG_LBC_LCRR		0x00030004	/* local bus freq 	*/
+#define CFG_LBC_LBCR		0x00000000
+#define CFG_LBC_LSRT		0x20000000
+#define CFG_LBC_MRTPR		0x20000000
+#define CFG_LBC_LSDMR_1		0x2861b723
+#define CFG_LBC_LSDMR_2		0x0861b723
+#define CFG_LBC_LSDMR_3		0x0861b723
+#define CFG_LBC_LSDMR_4		0x1861b723
+#define CFG_LBC_LSDMR_5		0x4061b723
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#else
+#define CFG_BR4_PRELIM          0xfc000801      /* 32KB, 8-bit wide for ADS config reg */
+#endif
+#define CFG_OR4_PRELIM		0xffffe1f1
+#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR       0x40000000      /* Initial RAM address  */
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_ON_SCC              	/* define if console on SCC */
+#undef  CONFIG_CONS_NONE                	/* define if console on something else */
+#define CONFIG_CONS_INDEX       1       	/* which serial channel for console */
+
+#define CONFIG_BAUDRATE	 	115200
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C    		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
+
+#define CFG_PCI_MEM_BASE	0xe0000000
+#define CFG_PCI_MEM_PHYS	0xe0000000
+#define CFG_PCI_MEM_SIZE	0x10000000
+
+#if defined(CONFIG_PCI) 		/* PCI Ethernet card */
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+  #if !defined(CONFIG_PCI_PNP)
+  #define PCI_ENET0_IOADDR    	0xe0000000
+  #define PCI_ENET0_MEMADDR     0xe0000000
+  #define PCI_IDSEL_NUMBER      0x0c 	/* slot0->3(IDSEL)=12->15 */
+  #endif
+#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#if defined(CONFIG_MPC85xx_REV1) 	/* Errata PCI 7 */
+  #define CFG_PCI_SUBSYS_DEVICEID 0x0003
+#else
+  #define CFG_PCI_SUBSYS_DEVICEID 0x0009
+#endif
+#elif defined(CONFIG_TSEC_ENET) 	/* TSEC Ethernet port */
+#define CONFIG_NET_MULTI 	1
+#define CONFIG_PHY_M88E1011      1       /* GigaBit Ether PHY        */
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		8	/* PHY address			*/
+#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+#define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
+#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
+#define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
+  #if (CONFIG_ETHER_INDEX == 2)
+  /*
+   * - Rx-CLK is CLK13
+   * - Tx-CLK is CLK14
+   * - Select bus for bd/buffers
+   * - Full duplex
+   */
+  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CFG_CPMFCR_RAMTYPE    0
+  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
+  #define FETH2_RST		0x01
+  #elif (CONFIG_ETHER_INDEX == 3)
+  /* need more definitions here for FE3 */
+  #define FETH3_RST		0x80
+  #endif  				/* CONFIG_ETHER_INDEX */
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	2		/* Port C */
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+#endif
+
+/* Environment */
+#ifndef CFG_RAMBOOT
+  #if defined(CONFIG_RAM_AS_FLASH)
+  #define CFG_ENV_IS_NOWHERE
+  #define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
+  #define CFG_ENV_SIZE		0x2000
+  #else
+  #define CFG_ENV_IS_IN_FLASH	1
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+  #define CFG_ENV_SECT_SIZE	0x40000	/* 128K(one sector) for env */
+  #endif
+  #define CFG_ENV_SIZE		0x2000
+#else
+#define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200"
+/*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
+#define CONFIG_BOOTCOMMAND	"bootm 0xff400000 0xff700000"
+#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+  #if defined(CONFIG_PCI)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				 ~(CFG_CMD_ENV | \
+				  CFG_CMD_LOADS ))
+  #elif defined(CONFIG_TSEC_ENET)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING | \
+				CFG_CMD_I2C ) & \
+				~(CFG_CMD_ENV))
+  #elif defined(CONFIG_ETHER_ON_FCC)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				~(CFG_CMD_ENV))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C)
+  #elif defined(CONFIG_TSEC_ENET)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | \
+				CFG_CMD_I2C)
+  #elif defined(CONFIG_ETHER_ON_FCC)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C)
+  #endif
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"MPC8560ADS=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x1000000	/* default load address */
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_ETHADDR  00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
+#endif
+
+#define CONFIG_SERVERIP 	163.12.64.52
+#define CONFIG_IPADDR  		10.82.0.105
+#define CONFIG_GATEWAYIP	10.82.1.254
+#define CONFIG_NETMASK		255.255.254.0
+#define CONFIG_HOSTNAME 	MPC8560ADS_PILOT_003
+#define CONFIG_ROOTPATH 	/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
+#define CONFIG_BOOTFILE 	pImage
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index 3bf54d2eb9d..7a1cc7e898f 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -402,7 +402,7 @@
 #define CFG_BR5_ISP1362		((CFG_ISP1362_BASE & BR_BA_MSK) | \
 				 BR_PS_16          | BR_MS_GPCM | BR_V )
 #endif	/* CONFIG_ISP1362_USB */
-				 
+
 /*
  * Memory Periodic Timer Prescaler
  *
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 1630bc32b19..ca045ad2702 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -31,7 +31,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */	
+#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
 #define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
 #define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
 #ifndef	CONFIG_PPCHAMELEON_MODULE_MODEL
@@ -141,8 +141,8 @@
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE      \
-        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-         57600, 115200, 230400, 460800, 921600 }
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
@@ -184,79 +184,78 @@
 #define NAND_DISABLE_CE(nand) do \
 { \
 	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
-        { \
-            case CFG_NAND0_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
-                break; \
-            case CFG_NAND1_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
-                break; \
-        } \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+		break; \
+	} \
 } while(0)
 
 #define NAND_ENABLE_CE(nand) do \
 { \
 	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
-        { \
-            case CFG_NAND0_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
-                break; \
-            case CFG_NAND1_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
-                break; \
-        } \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+		break; \
+	} \
 } while(0)
 
 
-
 #define NAND_CTL_CLRALE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
-        { \
-            case CFG_NAND0_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
-                break; \
-            case CFG_NAND1_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
-                break; \
-        } \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+		break; \
+	} \
 } while(0)
 
 #define NAND_CTL_SETALE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
-        { \
-            case CFG_NAND0_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
-                break; \
-            case CFG_NAND1_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
-                break; \
-        } \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+		break; \
+	} \
 } while(0)
 
 #define NAND_CTL_CLRCLE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
-        { \
-            case CFG_NAND0_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
-                break; \
-            case CFG_NAND1_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
-                break; \
-        } \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+		break; \
+	} \
 } while(0)
 
 #define NAND_CTL_SETCLE(nandptr) do { \
 	switch((unsigned long)nandptr) { \
-        case CFG_NAND0_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
-                break; \
-        case CFG_NAND1_BASE: \
-                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
-                break; \
-        } \
+	case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+		break; \
+	case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+		break; \
+	} \
 } while(0)
 
 #ifdef NAND_NO_RB
@@ -285,7 +284,7 @@
 #define CONFIG_PCI			/* include pci support	        */
 #define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
 #undef  CONFIG_PCI_PNP			/* do pci plug-and-play         */
-                                        /* resource configuration       */
+					/* resource configuration       */
 
 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
@@ -349,7 +348,7 @@
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
-                                   /* total size of a CAT24WC16 is 2048 bytes */
+				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
 #define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
@@ -375,7 +374,7 @@
  * Cache Configuration
  */
 #define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
-                                        /* have only 8kB, 16kB is save here     */
+					/* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -659,23 +658,23 @@
 !-----------------------------------------------------------------------
 */
 #define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
-                              PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
-                              PLL_MALDIV_1 | PLL_PCIDIV_4)
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_133_66_66_33  (PLL_FBKDIV_4  |  \
-                              PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
-                              PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+			      PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-                              PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
-                              PLL_MALDIV_1 | PLL_PCIDIV_4)
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
-                              PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-                              PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-                              PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
-                              PLL_MALDIV_1 | PLL_PCIDIV_4)
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
-                              PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-                              PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #if 0 /* test-only */
 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
index 535ec798517..7b9fdc4e703 100644
--- a/include/configs/TOP860.h
+++ b/include/configs/TOP860.h
@@ -275,7 +275,7 @@
  *	1	CSR		0			Checkstop reset enable
  *	1	LOLRE	0			Loss-of-lock reset enable
  *	1	FIOPD	0			Force I/O pull down
- *	5	0		00000			
+ *	5	0		00000
  */
 #define CFG_PLPRCR	(PLPRCR_TEXPS | ((CFG_MF-1)<<20))
 
@@ -322,8 +322,8 @@
  *	1	SEME	0			Sync external master enable
  *	1	BSC		0			Byte strobe configuration
  *	1	GB5E	0			GPL_B5 enable
- *	1	B2DD	0			Bank 2 double drive			
- *	1	B3DD	0			Bank 3 double drive			
+ *	1	B2DD	0			Bank 2 double drive
+ *	1	B3DD	0			Bank 3 double drive
  *	4	0		0000
  */
 #define CFG_SIUMCR	(SIUMCR_MLRC11)
@@ -412,7 +412,7 @@
 #define CONFIG_BOOTP_MASK				( CONFIG_BOOTP_DEFAULT		| \
 									  	  CONFIG_BOOTP_BOOTFILESIZE   \
 										)
-										
+
 
 /*
  * Set default IP stuff just to get bootstrap entries into the
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
index 3d814d014c0..1862b06a03d 100644
--- a/include/configs/ixdp425.h
+++ b/include/configs/ixdp425.h
@@ -68,7 +68,7 @@
 #define CONFIG_SERVERIP         192.168.0.250
 #define CONFIG_BOOTCOMMAND      "bootm 50040000"
 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG      
+#define CONFIG_CMDLINE_TAG
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
@@ -93,7 +93,7 @@
 #define CFG_LOAD_ADDR           0x00010000      /* default load address */
 
 #define CFG_HZ                  3333333         /* spec says 66.666 MHz, but it appears to be 33 */
-                                                /* valid baudrates */
+						/* valid baudrates */
 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h
index dfcb3672f20..2658135e945 100644
--- a/include/configs/omap1510.h
+++ b/include/configs/omap1510.h
@@ -533,7 +533,6 @@ typedef struct {
 #define WDTIM_CONTROL_ST	BIT7
 
 
-
 /* ---------------------------------------------------------------------------
  *  Differentiating processor versions for those who care.
  * ---------------------------------------------------------------------------
diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h
index 55fad43a444..d65e2a01d6f 100644
--- a/include/configs/omap1610inn.h
+++ b/include/configs/omap1610inn.h
@@ -67,7 +67,7 @@
 #define CFG_NS16550_SERIAL
 #define CFG_NS16550_REG_SIZE	(-4)
 #define CFG_NS16550_CLK	(48000000)	/* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart 
+#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart
 						on helen */
 
 /*
@@ -120,7 +120,7 @@
 
 #define CFG_LOAD_ADDR	0x10000000	/* default load address */
 
-/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by 
+/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
  * DPLL1. This time is further subdivided by a local divisor.
  */
 #define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index cc4936677d5..4411a11398a 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -473,13 +473,13 @@
 /* Add support for a few extra bootp options like:
  *	- File size
  *	- DNS (up to 2 servers)
- *      - Send hostname to DHCP server 
+ *      - Send hostname to DHCP server
  */
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_BOOTFILESIZE | \
 				 CONFIG_BOOTP_DNS | \
-                                 CONFIG_BOOTP_DNS2 | \
-                                 CONFIG_BOOTP_SEND_HOSTNAME)
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME)
 
 /* undef this to save memory */
 #define CFG_LONGHELP
@@ -497,7 +497,7 @@
  */
 #define CONFIG_TIMESTAMP
 
-/* If this variable is defined, an environment variable named "ver" 
+/* If this variable is defined, an environment variable named "ver"
  * is created by U-Boot showing the U-Boot version.
  */
 #define CONFIG_VERSION_VARIABLE
@@ -553,40 +553,40 @@
  * Miscellaneous configurable options
  */
 #define CFG_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
-                                        /* in the bootm command.             */
+					/* in the bootm command.             */
 #define CFG_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
-                                        /* "## <message>" from the bootm cmd */
+					/* "## <message>" from the bootm cmd */
 #define CFG_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
-                                        /* defined, then the hostname param  */
-                                        /* validated against checkhostname.  */
+					/* defined, then the hostname param  */
+					/* validated against checkhostname.  */
 #define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
 #define CFG_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
-                                        /* (limited to maximum of 1024 msec) */
+					/* (limited to maximum of 1024 msec) */
 #define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
-                                        /* Check for abort key presses       */
-                                        /* at least once in dependent of the */
-                                        /* CONFIG_BOOTDELAY value.           */
+					/* Check for abort key presses       */
+					/* at least once in dependent of the */
+					/* CONFIG_BOOTDELAY value.           */
 #define CFG_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
 #define CFG_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
-                                        /* state to the fault LED.           */
+					/* state to the fault LED.           */
 #define CFG_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
-                                        /* the Ethernet link state.          */
+					/* the Ethernet link state.          */
 #define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
-                                        /* until the TFTP is successful.     */
+					/* until the TFTP is successful.     */
 #define CFG_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
-                                        /* turn off the STATUS LEDs.         */
+					/* turn off the STATUS LEDs.         */
 #define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
-                                        /* incoming data.                    */
+					/* incoming data.                    */
 #define CFG_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
-                                        /* to signify that tftp is moving.   */
+					/* to signify that tftp is moving.   */
 #define CFG_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
- 				        /* flash the status LED.             */
+					/* flash the status LED.             */
 #define CFG_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
-                                        /* during the tftp file transfer.    */
+					/* during the tftp file transfer.    */
 #define CFG_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
-                                        /* '#'s from the tftp command.       */
+					/* '#'s from the tftp command.       */
 #define CFG_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
-                                        /* issued during the tftp command.   */
+					/* issued during the tftp command.   */
 #define CFG_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
 					/* before it gives up.               */
 
@@ -796,7 +796,7 @@
 			 SYPCR_LBME |\
 			 SYPCR_SWRI |\
 			 SYPCR_SWP  |\
-                         SYPCR_SWE)
+			 SYPCR_SWE)
 #else
 #define CFG_SYPCR	(SYPCR_SWTC |\
 			 SYPCR_BMT  |\
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 0e6ffd90ba1..caf1bbd0dc8 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -334,7 +334,7 @@
 
 /*-----------------------------------------------------------------------
  * burn-in test stuff.
- *  
+ *
  * BURN_IN_CYCLE_DELAY defines the seconds to wait between each burn-in cycle
  * Because the burn-in test itself causes also an delay of about 4 seconds,
  * this time must be subtracted from the desired overall burn-in cycle time.