diff options
| author | Ye Li <ye.li@nxp.com> | 2018-08-09 03:10:02 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-08-10 03:11:00 -0700 |
| commit | 8efc764dffc4c32187d65123f52030c28930a1ee (patch) | |
| tree | 5d89931bec3e931a3accd1a5444e1b85d8ad208b /include/configs | |
| parent | cdedbb42e052d4bb3ff6b45044dd0d6023f3cb20 (diff) | |
MLK-19177 imx8dx: Add iMX8DX DDR3 ARM2 board support
Add new dts, config and defconfig file for DX DDR3 ARM2 board. Since
it does not have USB3.0 and SD, disable them in DTS and header file. Also move
gpio expander to i2c1 according with its schematic.
In defconfig, fastboot is default enabled due to we need uuu to program
eMMC.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e5b822615a5aa2fadb481002c286f35d996999f8)
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/imx8qxp_arm2.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/include/configs/imx8qxp_arm2.h b/include/configs/imx8qxp_arm2.h index 9d7bb715f9..564f265354 100644 --- a/include/configs/imx8qxp_arm2.h +++ b/include/configs/imx8qxp_arm2.h @@ -118,7 +118,9 @@ "\0" \ "initrd_addr=0x83100000\0" \ "initrd_high=0xffffffff\0" \ - "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + "bootcmd_mfg=run mfgtool_args; if iminfo ${initrd_addr}; then "\ + "booti ${loadaddr} ${initrd_addr} ${fdt_addr};"\ + "else fastboot 1; fi\0" \ /* Initial environment variables */ #ifdef CONFIG_NAND_BOOT @@ -262,9 +264,15 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ +#ifdef CONFIG_TARGET_IMX8DX_DDR3_ARM2 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) @@ -273,7 +281,7 @@ #define CONFIG_NR_DRAM_BANKS 3 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 -#ifdef CONFIG_TARGET_IMX8QXP_DDR3_ARM2 +#if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2) || defined(CONFIG_TARGET_IMX8DX_DDR3_ARM2) #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ /* LPDDR4 board total DDR is 3GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 @@ -371,4 +379,7 @@ #define BOOTAUX_RESERVED_MEM_BASE 0x88000000 #define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */ +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG + #endif /* __IMX8QXP_ARM2_H */ |