diff options
| author | Dalon Westergreen <dwesterg@gmail.com> | 2018-09-10 10:28:48 -0700 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-09-15 03:17:01 +0200 |
| commit | 3570469742aec30fed0b423708df346176fa9438 (patch) | |
| tree | 996a70e1a7a48eefae99200cc38cd6891a6eb0cb /include/configs/socfpga_stratix10_socdk.h | |
| parent | 2ff60af605d64218374dbaf71cf47be865f84192 (diff) | |
arm: socfpga: stratix10: add CONFIG_SPL_TARGET
Stratix10 combines the u-boot-spl image into the fpga configuration
bitstream so that the SDM can load the processors memory. This
process requires a hex format of the u-boot-spl image.
CONFIG_SPL_TARGET is set to "spl/u-boot-spl.hex"
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Diffstat (limited to 'include/configs/socfpga_stratix10_socdk.h')
| -rw-r--r-- | include/configs/socfpga_stratix10_socdk.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index b58f478004..91315a0031 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -202,6 +202,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) * */ +#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |