diff options
| author | Tom Rini <trini@konsulko.com> | 2020-04-07 11:58:44 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-07 17:13:35 -0400 |
| commit | 1f47e2aca42c2e51ff3a7754c717ee13f568c721 (patch) | |
| tree | eca6cb5e551dbb75c2328b1dba3e7a2b8a77d327 /include/configs/socfpga_common.h | |
| parent | 2b18b89156335bf1f0d84f81d3597762bc48c61d (diff) | |
| parent | 895a7866c20cf6c01779b5a60fbf2770b88930a4 (diff) | |
Merge tag 'xilinx-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2020.07
common:
- Align ENV_FAT_INTERFACE
- Fix MAC address source print log
- Improve based autodetection code
xilinx:
- Enable netconsole
Microblaze:
- Setup default ENV_OFFSET/ENV_SECT_SIZE
Zynq:
- Multiple DT updates/fixes
- Use DEVICE_TREE environment variable for DTB selection
- Switch to single zynq configuration
- Enable NOR flash via DM
- Minor SPL print removal
- Enable i2c mux driver
ZynqMP:
- Print multiboot register
- Enable cache commands in mini mtest
- Multiple DT updates/fixes
- Fix firmware probing when driver is not enabled
- Specify 3rd backup RAM boot mode in SPL
- Add SPL support for zcu102 v1.1 and zcu111 revA
- Redesign debug uart enabling and psu_init delay
- Enable full u-boot run from EL3
- Enable u-boot.itb generation without ATF with U-Boot in EL3
Versal:
- Enable distro default
- Enable others SPI flashes
- Enable systems without DDR
Drivers:
- Gem:
- Flush memory after freeing
- Handle mdio bus separately
- Watchdog:
- Get rid of unused global data pointer
- Enable window watchdog timer
- Serial:
- Change reinitialization logic in zynq serial driver
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs/socfpga_common.h')
| -rw-r--r-- | include/configs/socfpga_common.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index ec41843695..410ec80618 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -21,14 +21,15 @@ #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ #ifndef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 #endif -#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE) #endif |