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authorwdenk <wdenk>2003-08-28 09:41:22 +0000
committerwdenk <wdenk>2003-08-28 09:41:22 +0000
commitd94f92cbd7f4a4d3bf0d5d963b709c686e8f6633 (patch)
treec85dd4a10c5a68ca09b9139c1b6428d55ada6451 /include/configs/rmu.h
parente0ac62d798ce60ec5d43125d4786e58b0d881836 (diff)
* Fix ICU862 environment problem
* Fix RAM size detection for RMU board * Implement "reset" for MGT5100/MPC5200 systems
Diffstat (limited to 'include/configs/rmu.h')
-rw-r--r--include/configs/rmu.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
index 0a94714f7be..7b33c7e1b15 100644
--- a/include/configs/rmu.h
+++ b/include/configs/rmu.h
@@ -291,12 +291,12 @@
*
*/
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
-#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
+#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM 0x00000E00
-#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
/* RPXLITE mem setting */
@@ -321,8 +321,8 @@
* MAMR settings for SDRAM
*/
-/* 10 column SDRAM */
-#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)