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authorAndreas Müller <schnitzeltony@gmx.de>2012-01-04 15:26:21 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-01-16 08:40:12 +0100
commit0f8d3eb902a497418fdb935236ff9219e2cea1be (patch)
treefad0e1fb32dc4508557fb93dbc3966ce7225324a /include/configs/omap3_overo.h
parentbae485db1245fc142acb85bac25e42f2898f82ae (diff)
include/configs/omap3_overo.h: several cleanups
* remove unused macros * remove unused macro values * align tabs * remove Free Software Foundation address Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
Diffstat (limited to 'include/configs/omap3_overo.h')
-rw-r--r--include/configs/omap3_overo.h66
1 files changed, 31 insertions, 35 deletions
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index db453acee1..8f2e69daa5 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -13,8 +13,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc.
*/
#ifndef __CONFIG_H
@@ -23,41 +22,41 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3_OVERO 1 /* working with overo */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP3_OVERO /* working with overo */
-#define CONFIG_SDRC /* The chip has SDRC controller */
+#define CONFIG_SDRC /* The chip has SDRC controller */
-#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/*
* Display CPU and Board information
*/
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
+#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
-#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_LIBFDT
/*
* Size of malloc() pool
*/
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* Hardware drivers
@@ -66,7 +65,7 @@
/*
* NS16550 Configuration
*/
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
@@ -85,10 +84,10 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
/* commands to include */
#include <config_cmd_default.h>
@@ -110,31 +109,29 @@
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C 1
+#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
-#define CONFIG_I2C_MULTI_BUS 1
-#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_DRIVER_OMAP34XX_I2C
/*
* TWL4030
*/
-#define CONFIG_TWL4030_POWER 1
-#define CONFIG_TWL4030_LED 1
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_QUIET_TEST 1
+#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand */
/* at CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
@@ -246,7 +243,6 @@
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*-----------------------------------------------------------------------
@@ -269,7 +265,7 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_IS_IN_NAND
#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
@@ -283,9 +279,9 @@
*----------------------------------------------------------------------------
*/
-#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SMC911X_BASE 0x2C000000
+#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */