keymile: Fix Coding style issues for keymile boards.

- use I/O accessors
  -> For accessing the FPGA therefore a struct km_bec_fpga
     is introduced.
- no longer externs needed
- to defines, that only select functions, don;t assign a
  numeric value
- Codingstyle changes to prevent checkpatch errors/warnings

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
cc: Detlev Zundel <dzu@denx.de>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>

1 files changed, 63 insertions, 44 deletions

diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index f1bd32a31e2..d0b7c651a20 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -29,15 +29,12 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8247		1
-#define CONFIG_MPC8272_FAMILY   1
-#define CONFIG_MGCOGE		1
+#define CONFIG_MPC8247
+#define CONFIG_MGCOGE
 #define CONFIG_HOSTNAME		mgcoge
 
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
 
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"
 
@@ -69,13 +66,13 @@
 #define	CONFIG_ETHER_ON_SCC		/* Ethernet is on SCC */
 #undef	CONFIG_ETHER_ON_FCC		/* Ethernet is not on FCC     */
 #undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
-#define CONFIG_NET_MULTI	1
+#define CONFIG_NET_MULTI
 
 #define CONFIG_ETHER_INDEX	4
 #define CONFIG_HAS_ETH0
 #define CONFIG_SYS_SCC_TOUT_LOOP	10000000
 
-# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
+# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
 
 #ifndef CONFIG_8260_CLKIN
 #define CONFIG_8260_CLKIN	66000000	/* in Hz */
@@ -113,8 +110,9 @@
 #define CONFIG_SYS_FLASH_SIZE		32
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max num of flash banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	3
+/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
 
 #define CONFIG_SYS_FLASH_BASE_1	0x50000000
 #define CONFIG_SYS_FLASH_SIZE_1	32
@@ -130,24 +128,26 @@
 #define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384KB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)
 
 #define CONFIG_ENV_IS_IN_FLASH
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
 
 /* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
-#define CONFIG_ENV_BUFFER_PRINT		1
+#define CONFIG_ENV_BUFFER_PRINT
 
 /* enable I2C and select the hardware/software driver */
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
@@ -159,15 +159,23 @@
 #define I2C_ACTIVE	(iop->pdir |=  0x00010000)
 #define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
 #define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
+#define I2C_SDA(bit)	do { \
+				if (bit) \
+					iop->pdat |=  0x00010000; \
+				else \
+					iop->pdat &= ~0x00010000; \
+			} while (0)
+#define I2C_SCL(bit)	do { \
+				if (bit) \
+					iop->pdat |=  0x00020000; \
+				else \
+					iop->pdat &= ~0x00020000; \
+			} while (0)
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
-/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
-#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
-#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75		/* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses */
 #define CONFIG_SYS_DTT_MAX_TEMP	70
 #define CONFIG_SYS_DTT_LOW_TEMP	-30
 #define CONFIG_SYS_DTT_HYSTERESIS	3
@@ -178,8 +186,9 @@
 #define CONFIG_SYS_IMMR		0xF0000000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
@@ -194,11 +203,11 @@
 #define CONFIG_SYS_HRCW_SLAVE6		0
 #define CONFIG_SYS_HRCW_SLAVE7		0
 
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
 
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5 /* log base 2 of the above value */
 #endif
 
 #define CONFIG_SYS_HID0_INIT		0
@@ -211,14 +220,16 @@
 #define CONFIG_SYS_BCR			0x10000000
 #define CONFIG_SYS_SCCR		(SCCR_PCI_MODE | SCCR_PCI_MODCK)
 
-/*-----------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
 #define CONFIG_SYS_RMR         0
 
-/*-----------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------
  * TMCNTSC - Time Counter Status and Control                     4-40
  *-----------------------------------------------------------------------
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
@@ -226,7 +237,8 @@
  */
 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
-/*-----------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
@@ -234,7 +246,8 @@
  */
 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
-/*-----------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
@@ -265,14 +278,16 @@
 			 ORxG_TRLX )
 
 
-/* Bank 1 - 60x bus SDRAM
+/*
+ * Bank 1 - 60x bus SDRAM
  */
 #define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)
 
 #define CONFIG_SYS_MPTPR       0x1800
 
-/*-----------------------------------------------------------------------------
+/*
+ *-----------------------------------------------------------------------------
  * Address for Mode Register Set (MRS) command
  *-----------------------------------------------------------------------------
  */
@@ -286,8 +301,9 @@
 
 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1
 
-/* SDRAM initialization values
-*/
+/*
+ * SDRAM initialization values
+ */
 
 #define CONFIG_SYS_OR1    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_8                     |\
@@ -304,8 +320,9 @@
 			 PSDMR_WRC_1C                   |\
 			 PSDMR_CL_2)
 
-/* GPIO/PIGGY on CS3 initialization values
-*/
+/*
+ * GPIO/PIGGY on CS3 initialization values
+ */
 #define CONFIG_SYS_PIGGY_BASE	0x30000000
 #define CONFIG_SYS_PIGGY_SIZE	128
 
@@ -316,8 +333,9 @@
 			 ORxG_CSNT | ORxG_ACS_DIV2 |\
 			 ORxG_SCY_3_CLK | ORxG_TRLX )
 
-/* Board FPGA on CS4 initialization values
-*/
+/*
+ * Board FPGA on CS4 initialization values
+ */
 #define CONFIG_SYS_FPGA_BASE	0x40000000
 #define CONFIG_SYS_FPGA_SIZE	1 /*1KB*/
 
@@ -328,8 +346,9 @@
 			 ORxG_CSNT | ORxG_ACS_DIV2 |\
 			 ORxG_SCY_3_CLK | ORxG_TRLX )
 
-/* CFG-Flash on CS5 initialization values
-*/
+/*
+ * CFG-Flash on CS5 initialization values
+ */
 #define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 			 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 
@@ -338,12 +357,12 @@
 				 ORxG_CSNT | ORxG_ACS_DIV2 |\
 				 ORxG_SCY_5_CLK | ORxG_TRLX )
 
-#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address */
 
 /* pass open firmware flat tree */
-#define CONFIG_FIT		1
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_FIT
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
 
 #define OF_TBCLK		(bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH		"/soc/cpm/serial@11a90"