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| author | Tom Rini <trini@konsulko.com> | 2022-05-27 10:19:45 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-06-06 12:09:28 -0400 |
| commit | 6600b355c71e80c99d8edb8603dd5e3df8ed4db8 (patch) | |
| tree | d1179e1dd0a4be5ae68ab05cd635ce7e1b38f824 /include/configs/j721e_evm.h | |
| parent | 55cf860ba7d604081b11b8ddc23c79572a0ada34 (diff) | |
Convert CONFIG_SPL_BSS_START_ADDR to Kconfig
This converts the following to Kconfig:
CONFIG_SPL_BSS_START_ADDR
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs/j721e_evm.h')
| -rw-r--r-- | include/configs/j721e_evm.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index ba3f9de6bf..8e7861fc91 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -24,15 +24,6 @@ /* Image load address in RAM for DFU boot*/ #else #define CONFIG_SYS_UBOOT_BASE 0x50080000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ - CONFIG_SPL_BSS_MAX_SIZE) /* Set the stack right below the SPL BSS section */ /* Configure R5 SPL post-relocation malloc pool in DDR */ #define CONFIG_SYS_SPL_MALLOC_START 0x84000000 |