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authorBin Meng <bmeng.cn@gmail.com>2015-05-25 22:35:06 +0800
committerSimon Glass <sjg@chromium.org>2015-06-04 02:39:39 -0600
commit05b98ec3468547057666dd685b2a1615298c24cc (patch)
treef6b4914a6cc6423e573dbf059ce8b8ae057f1659 /include/configs/galileo.h
parent5910955f3cf685c1ca4e4abd1546fc59da55239a (diff)
x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/galileo.h')
-rw-r--r--include/configs/galileo.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 083d8b41051..fd89bf30ef3 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_MISC_INIT
#define CONFIG_X86_SERIAL