diff options
author | Paul Burton <paul.burton@mips.com> | 2017-11-21 11:18:39 -0800 |
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committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2017-11-28 21:59:30 +0100 |
commit | cc4f36435fb39c8c89aa6cfc9c0ffb680727352d (patch) | |
tree | 79770febd4fad22fe90a7eaa69fc37cee5aa62ae /include/configs/boston.h | |
parent | d8b326976a44f185c52255458142086e0e8a7c34 (diff) |
MIPS: Break out of cache loops for unimplemented caches
If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Diffstat (limited to 'include/configs/boston.h')
0 files changed, 0 insertions, 0 deletions