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authorHeiko Schocher <hs@denx.de>2015-05-18 13:32:31 +0200
committerStefano Babic <sbabic@denx.de>2015-05-26 14:18:11 +0200
commit7254d92ebcedf9dc8dfe76a8d310faf46f46274f (patch)
treee84786aa5762494da6a6524ae92dd9f35d17d394 /include/configs/aristainetos-common.h
parente6c8b716c7035fd2b80d0b938e736176053b9ef6 (diff)
arm, imx6: add support for aristainetos2 board
add support for imx6dl based aristainetos2 board U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27) CPU: Freescale i.MX6DL rev1.1 at 792 MHz Reset cause: WDOG Board: aristaitenos2 Watchdog enabled I2C: ready DRAM: 1 GiB NAND: 1024 MiB MMC: FSL_SDHC: 0 SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB Display: lg4573 (480x800) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'include/configs/aristainetos-common.h')
-rw-r--r--include/configs/aristainetos-common.h333
1 files changed, 333 insertions, 0 deletions
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
new file mode 100644
index 0000000000..7d60cf9840
--- /dev/null
+++ b/include/configs/aristainetos-common.h
@@ -0,0 +1,333 @@
+/*
+ * (C) Copyright 2015
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ARISTAINETOS_COMMON_CONFIG_H
+#define __ARISTAINETOS_COMMON_CONFIG_H
+
+#define CONFIG_MX6
+
+#include "mx6_common.h"
+#include <linux/sizes.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_MACH_TYPE 4501
+#define CONFIG_MMCROOT "/dev/mmcblk0p1"
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MTD
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 3
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SETEXPR
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=u-boot.scr\0" \
+ "fit_file=/boot/system.itb\0" \
+ "loadaddr=0x12000000\0" \
+ "fit_addr_r=0x14000000\0" \
+ "uboot=/boot/u-boot.imx\0" \
+ "uboot_sz=d0000\0" \
+ "rescue_sys_addr=f0000\0" \
+ "rescue_sys_length=f10000\0" \
+ "panel=lb07wv8\0" \
+ "splashpos=m,m\0" \
+ "console=" CONFIG_CONSOLE_DEV "\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
+ "default ${board_type}\0" \
+ "get_env=mw ${loadaddr} 0 0x20000;" \
+ "mmc rescan;" \
+ "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
+ "env import -t ${loadaddr}\0" \
+ "default_env=mw ${loadaddr} 0 0x20000;" \
+ "env export -t ${loadaddr} serial# ethaddr eth1addr " \
+ "board_type panel;" \
+ "env default -a;" \
+ "env import -t ${loadaddr}\0" \
+ "loadbootscript=" \
+ "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "mmcpart=1\0" \
+ "mmcdev=0\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs addmtd addmisc set_fit_default;" \
+ "bootm ${fit_addr_r}\0" \
+ "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
+ "${fit_file}\0" \
+ "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+ "${uboot}\0" \
+ "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
+ "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
+ "setexpr uboot_maxsize ${uboot_sz} - 400;" \
+ "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
+ "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
+ "sf write ${loadaddr} 400 ${filesize};" \
+ "sf read ${cmp_buf} 400 ${uboot_sz};" \
+ "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
+ "ubiboot=echo Booting from ubi ...; " \
+ "run ubiargs addmtd addmisc set_fit_default;" \
+ "bootm ${fit_addr_r}\0" \
+ "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \
+ "ubifsload ${fit_addr_r} /boot/system.itb; " \
+ "imi ${fit_addr_r}\0 " \
+ "rescueargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/ram rw\0 " \
+ "rescueboot=echo Booting rescue system from NOR ...; " \
+ "run rescueargs addmtd addmisc set_fit_default;" \
+ "bootm ${fit_addr_r}\0" \
+ "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
+ "${rescue_sys_length}; imi ${fit_addr_r}\0" \
+ CONFIG_EXTRA_ENV_BOARD_SETTINGS
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run mmc_load_fit; then " \
+ "run mmcboot; " \
+ "else " \
+ "if run ubifs_load_fit; then " \
+ "run ubiboot; " \
+ "else " \
+ "if run rescue_load_fit; then " \
+ "run rescueboot; " \
+ "else " \
+ "echo RESCUE SYSTEM BOOT " \
+ "FAILURE;" \
+ "fi; " \
+ "fi; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "if run ubifs_load_fit; then " \
+ "run ubiboot; " \
+ "else " \
+ "if run rescue_load_fit; then " \
+ "run rescueboot; " \
+ "else " \
+ "echo RESCUE SYSTEM BOOT FAILURE;" \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (12 * 1024)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SECT_SIZE (0x010000)
+#define CONFIG_ENV_OFFSET (0x0d0000)
+#define CONFIG_ENV_OFFSET_REDUND (0x0e0000)
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0x7f
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }
+
+#define CONFIG_CMD_GPIO
+
+/* NAND stuff */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_RTC_BUS_NUM 2
+#define CONFIG_RTC_M41T11
+#define CONFIG_CMD_DATE
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+/* UBI support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+
+#define CONFIG_FIT
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+/* check this console not needed, after test remove it */
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 198000000
+#define CONFIG_IMX_VIDEO_SKIP
+
+#define CONFIG_CMD_BMP
+
+#define CONFIG_PWM_IMX
+#define CONFIG_IMX6_PWM_PER_CLK 66000000
+
+#endif /* __ARISTAINETOS_COMMON_CONFIG_H */