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authorBiwen Li <biwen.li@nxp.com>2020-05-01 20:04:21 +0800
committerPriyanka Jain <priyanka.jain@nxp.com>2020-05-04 09:12:36 +0530
commitd2e3f7c608b86fbbc027e46acb431abfba304333 (patch)
treed45a3d71f752a1ceec29b3dd22b90f9f999d8238 /include/configs/T104xRDB.h
parent613e66eb80c2cb0f9c1db408ecd4c08e8fae5790 (diff)
dm: powerpc: T1040/T1042: add i2c DM support
This supports i2c DM for SoC T1040/T1042 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'include/configs/T104xRDB.h')
-rw-r--r--include/configs/T104xRDB.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index bc65118657..7d15910f65 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*/
#ifndef __CONFIG_H
@@ -27,6 +28,7 @@
#define CONFIG_SPL_SKIP_RELOCATE
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_DM_I2C
#endif
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
@@ -459,8 +461,8 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#endif
/* I2C */
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C3_SPEED 400000
@@ -473,7 +475,12 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
+#endif
+#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x8
@@ -484,6 +491,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
/* LDI/DVI Encoder for display */
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
+#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
/*
* RTC configuration