rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

1 files changed, 90 insertions, 90 deletions

diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 2676d7d357f..e250e0338d5 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -33,7 +33,7 @@
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_PM520		1	/* ... on PM520 board */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
 
 #define CONFIG_MISC_INIT_R
 
@@ -47,7 +47,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 #ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
@@ -72,7 +72,7 @@
 #define CONFIG_NET_MULTI	1
 #define CONFIG_MII		1
 #define CONFIG_EEPRO100		1
-#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #undef  CONFIG_NS8382X
 
 #endif
@@ -161,42 +161,42 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x58
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR		0x51
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
 
 /*
  * Disk-On-Chip configuration
  */
 
-#define CFG_DOC_SHORT_TIMEOUT
-#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
 
-#define CFG_DOC_SUPPORT_2000
-#define CFG_DOC_SUPPORT_MILLENNIUM
-#define CFG_DOC_BASE		0xE0000000
-#define CFG_DOC_SIZE		0x00100000
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_BASE		0xE0000000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
 
 #if defined(CONFIG_BOOT_ROM)
 /*
@@ -208,10 +208,10 @@
  *               0xFD000000 for 16 MB
  *               0xFD800000 for  8 MB
  */
-#define CFG_FLASH_BASE		0xFA000000
-#define CFG_FLASH_SIZE		0x04000000
-#define CFG_BOOTROM_BASE	0xFFF00000
-#define CFG_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_FLASH_BASE		0xFA000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
+#define CONFIG_SYS_BOOTROM_BASE	0xFFF00000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
 #define CONFIG_ENV_ADDR		(0xFDF00000 + 0x40000)
 #else
 /*
@@ -223,19 +223,19 @@
  *               0xFF000000 for 16 MB
  *               0xFF800000 for  8 MB
  */
-#define CFG_FLASH_BASE		0xFC000000
-#define CFG_FLASH_SIZE		0x04000000
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
 #define CONFIG_ENV_ADDR		(0xFFF00000 + 0x40000)
 #endif
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
 
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
 
 #define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
 
@@ -253,27 +253,27 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xf0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
@@ -288,69 +288,69 @@
 /*
  * GPIO configuration
  */
-#define CFG_GPS_PORT_CONFIG	0x10000004
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
 #if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 #else
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 #endif
 
 #if defined(CONFIG_BOOT_ROM)
-#define CFG_BOOTCS_START	CFG_BOOTROM_BASE
-#define CFG_BOOTCS_SIZE		CFG_BOOTROM_SIZE
-#define CFG_BOOTCS_CFG		0x00047800
-#define CFG_CS0_START		CFG_BOOTROM_BASE
-#define CFG_CS0_SIZE		CFG_BOOTROM_SIZE
-#define CFG_CS1_START		CFG_FLASH_BASE
-#define CFG_CS1_SIZE		CFG_FLASH_SIZE
-#define CFG_CS1_CFG		0x0004FF00
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_BOOTROM_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_BOOTROM_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_BOOTROM_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_BOOTROM_SIZE
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_CFG		0x0004FF00
 #else
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x0004FF00
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
-#define CFG_CS1_START		CFG_DOC_BASE
-#define CFG_CS1_SIZE		CFG_DOC_SIZE
-#define CFG_CS1_CFG		0x00047800
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004FF00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_DOC_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_DOC_SIZE
+#define CONFIG_SYS_CS1_CFG		0x00047800
 #endif
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
 
 /*-----------------------------------------------------------------------
  * USB stuff
@@ -372,23 +372,23 @@
 #undef	CONFIG_IDE_RESET		/* reset for ide supported	*/
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	2	/* max. 2 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
 
 /* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
+#define CONFIG_SYS_ATA_STRIDE          4
 
 #endif /* __CONFIG_H */