diff options
| author | Simon Glass <sjg@chromium.org> | 2022-10-20 18:22:39 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-10-31 11:01:31 -0400 |
| commit | 984639039f4cfe32ec2cc531d6ace05326ac49eb (patch) | |
| tree | 472bf7e47978335a73c5d6025d3b83b534f7192b /include/configs/P2041RDB.h | |
| parent | 6f38d91158e7e4199753b79e0a25c1a65175aba4 (diff) | |
Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().
Rename it to resolve this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/configs/P2041RDB.h')
| -rw-r--r-- | include/configs/P2041RDB.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 925720d234..0ac7f161bc 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -12,13 +12,13 @@ #define __CONFIG_H #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc @@ -347,7 +347,7 @@ "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ "erase $ubootaddr +$filesize && " \ |