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authorBecky Bruce <becky.bruce@freescale.com>2008-11-05 14:55:35 -0600
committerJon Loeliger <jdl@freescale.com>2008-11-10 10:10:04 -0600
commitbf9a8c34309ed9276258295db9e9212aabb2531a (patch)
treea8a69bc73c806f02f1484ad253191d0eae5e552a /include/configs/MPC8610HPCD.h
parentc1e1cf69547b138173f87a7f81c42a5d8dbfde3d (diff)
mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY
We define CONFIG_MONITOR_BASE_EARLY to define the initial location of the bootpage in flash. Use this to create an early mapping definition for the FLASH, and change the early_bats code to use this. This change facilitates the relocation of the flash since the early mappings are no longer tied to the final location of the flash. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Diffstat (limited to 'include/configs/MPC8610HPCD.h')
-rw-r--r--include/configs/MPC8610HPCD.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 44867633667..f2fe4a6cf98 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -187,6 +187,7 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
@@ -419,6 +420,14 @@
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+ | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
+
/*
* BAT7 4M Cache-inhibited, guarded
* 0xe800_0000 4M PIXIS