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authorStefan Roese <sr@denx.de>2010-09-12 06:21:37 +0200
committerStefan Roese <sr@denx.de>2010-09-23 09:02:05 +0200
commitafabb498b749b48ca3ee7e833fe1501e2d6993cb (patch)
treea5e131d0d7f62e41bd9bc1c767452b43b75bf82e /include/configs/ASH405.h
parent5e7abce99163a00b8d267cc8045f06b498728288 (diff)
ppc4xx: Big header cleanup part 2, mostly PPC405 related
This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/ASH405.h')
-rw-r--r--include/configs/ASH405.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 4cb805223c..98bd6f32e5 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -335,12 +335,12 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
-#define CONFIG_SYS_GPIO0_OSRH 0x40000550
-#define CONFIG_SYS_GPIO0_OSRL 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
+#define CONFIG_SYS_GPIO0_OSRL 0x40000550
+#define CONFIG_SYS_GPIO0_OSRH 0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
#define CONFIG_SYS_GPIO0_TSRL 0x00000000
+#define CONFIG_SYS_GPIO0_TSRH 0x00000000
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)