diff options
author | Markus Klotzbuecher <mk@denx.de> | 2008-10-21 09:18:01 +0200 |
---|---|---|
committer | Markus Klotzbuecher <mk@denx.de> | 2008-10-21 09:18:01 +0200 |
commit | 50bd0057ba8fceeb48533f8b1a652ccd0e170838 (patch) | |
tree | ea1a183343573c2a48248923b96d316c0956727c /include/asm-ppc | |
parent | 9dbc366744960013965fce8851035b6141f3b3ae (diff) | |
parent | f82642e33899766892499b163e60560fbbf87773 (diff) |
Merge git://git.denx.de/u-boot into x1
Conflicts:
drivers/usb/usb_ohci.c
Diffstat (limited to 'include/asm-ppc')
-rw-r--r-- | include/asm-ppc/4xx_pcie.h | 14 | ||||
-rw-r--r-- | include/asm-ppc/cache.h | 11 | ||||
-rw-r--r-- | include/asm-ppc/cpm_8260.h | 8 | ||||
-rw-r--r-- | include/asm-ppc/fsl_ddr_dimm_params.h | 84 | ||||
-rw-r--r-- | include/asm-ppc/fsl_ddr_sdram.h | 12 | ||||
-rw-r--r-- | include/asm-ppc/global_data.h | 6 | ||||
-rw-r--r-- | include/asm-ppc/immap_85xx.h | 73 | ||||
-rw-r--r-- | include/asm-ppc/immap_86xx.h | 8 | ||||
-rw-r--r-- | include/asm-ppc/iopin_8260.h | 40 | ||||
-rw-r--r-- | include/asm-ppc/iopin_85xx.h | 40 | ||||
-rw-r--r-- | include/asm-ppc/iopin_8xx.h | 128 | ||||
-rw-r--r-- | include/asm-ppc/ppc4xx-sdram.h | 5 | ||||
-rw-r--r-- | include/asm-ppc/status_led.h | 6 | ||||
-rw-r--r-- | include/asm-ppc/u-boot.h | 6 |
14 files changed, 278 insertions, 163 deletions
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index a7cf1e8f5ee..a0e88de11d4 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -18,9 +18,9 @@ #define DCRN_SDR0_CFGDATA 0x00f #if defined(CONFIG_440SPE) -#define CFG_PCIE_NR_PORTS 3 +#define CONFIG_SYS_PCIE_NR_PORTS 3 -#define CFG_PCIE_ADDR_HIGH 0x0000000d +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 @@ -32,9 +32,9 @@ #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define CFG_PCIE_NR_PORTS 2 +#define CONFIG_SYS_PCIE_NR_PORTS 2 -#define CFG_PCIE_ADDR_HIGH 0x0000000d +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 @@ -44,9 +44,9 @@ #endif #if defined(CONFIG_405EX) -#define CFG_PCIE_NR_PORTS 2 +#define CONFIG_SYS_PCIE_NR_PORTS 2 -#define CFG_PCIE_ADDR_HIGH 0x00000000 +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000 #define DCRN_PCIE0_BASE 0x040 #define DCRN_PCIE1_BASE 0x060 @@ -406,7 +406,7 @@ static inline u32 sdr_base(int port) return PCIE0_SDR; case 1: return PCIE1_SDR; -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: return PCIE2_SDR; #endif diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 9d9b9717dde..7252be7db2d 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -19,10 +19,10 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* - * For compatibility reasons support the CFG_CACHELINE_SIZE too + * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too */ -#ifndef CFG_CACHELINE_SIZE -#define CFG_CACHELINE_SIZE L1_CACHE_BYTES +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES #endif #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) @@ -44,9 +44,10 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); extern void flush_dcache(void); extern void invalidate_dcache(void); -#ifdef CFG_INIT_RAM_LOCK +extern void invalidate_icache(void); +#ifdef CONFIG_SYS_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); -#endif /* CFG_INIT_RAM_LOCK */ +#endif /* CONFIG_SYS_INIT_RAM_LOCK */ #endif /* __ASSEMBLY__ */ /* prep registers for L2 */ diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h index 2a9774ade83..7e06940c971 100644 --- a/include/asm-ppc/cpm_8260.h +++ b/include/asm-ppc/cpm_8260.h @@ -141,16 +141,16 @@ typedef struct cpm_buf_desc { /* Parameter RAM offsets from the base. */ -#ifndef CFG_CPM_POST_WORD_ADDR +#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR #define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ #else -#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR +#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR #endif -#ifndef CFG_CPM_BOOTCOUNT_ADDR +#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) #else -#define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR +#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR #endif #define PROFF_SCC1 ((uint)0x8000) diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h new file mode 100644 index 00000000000..c794eedfe42 --- /dev/null +++ b/include/asm-ppc/fsl_ddr_dimm_params.h @@ -0,0 +1,84 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef DDR2_DIMM_PARAMS_H +#define DDR2_DIMM_PARAMS_H + +/* Parameters for a DDR2 dimm computed from the SPD */ +typedef struct dimm_params_s { + + /* DIMM organization parameters */ + char mpart[19]; /* guaranteed null terminated */ + + unsigned int n_ranks; + unsigned long long rank_density; + unsigned long long capacity; + unsigned int data_width; + unsigned int primary_sdram_width; + unsigned int ec_sdram_width; + unsigned int registered_dimm; + + /* SDRAM device parameters */ + unsigned int n_row_addr; + unsigned int n_col_addr; + unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ + unsigned int n_banks_per_sdram_device; + unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ + unsigned int row_density; + + /* used in computing base address of DIMMs */ + unsigned long long base_address; + + /* DIMM timing parameters */ + + /* + * SDRAM clock periods + * The range for these are 1000-10000 so a short should be sufficient + */ + unsigned int tCKmin_X_ps; + unsigned int tCKmin_X_minus_1_ps; + unsigned int tCKmin_X_minus_2_ps; + unsigned int tCKmax_ps; + + /* SPD-defined CAS latencies */ + unsigned int caslat_X; + unsigned int caslat_X_minus_1; + unsigned int caslat_X_minus_2; + + unsigned int caslat_lowest_derated; /* Derated CAS latency */ + + /* basic timing parameters */ + unsigned int tRCD_ps; + unsigned int tRP_ps; + unsigned int tRAS_ps; + + unsigned int tWR_ps; /* maximum = 63750 ps */ + unsigned int tWTR_ps; /* maximum = 63750 ps */ + unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns + = 511750 ps */ + + unsigned int tRRD_ps; /* maximum = 63750 ps */ + unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + unsigned int refresh_rate_ps; + + unsigned int tIS_ps; /* byte 32, spd->ca_setup */ + unsigned int tIH_ps; /* byte 33, spd->ca_hold */ + unsigned int tDS_ps; /* byte 34, spd->data_setup */ + unsigned int tDH_ps; /* byte 35, spd->data_hold */ + unsigned int tRTP_ps; /* byte 38, spd->trtp */ + unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tQHS_ps; /* byte 45, spd->tqhs */ +} dimm_params_t; + +extern unsigned int ddr_compute_dimm_parameters( + const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number); + +#endif diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 8adde34247b..c1ea7cd6bb1 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -36,6 +36,18 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #endif +/* define bank(chip select) interleaving mode */ +#define FSL_DDR_CS0_CS1 0x40 +#define FSL_DDR_CS2_CS3 0x20 +#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) +#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) + +/* define memory controller interleaving mode */ +#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 +#define FSL_DDR_PAGE_INTERLEAVING 0x1 +#define FSL_DDR_BANK_INTERLEAVING 0x2 +#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 4331a154ea6..aade097fa4e 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -33,7 +33,7 @@ * global variables during system initialization (until we have set * up the memory controller so that we can use RAM). * - * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) */ typedef struct global_data { @@ -129,14 +129,14 @@ typedef struct global_data { unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long have_console; /* serial_init() was called */ -#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2) +#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2) unsigned int dp_alloc_base; unsigned int dp_alloc_top; #endif #if defined(CONFIG_4xx) u32 uart_clk; #endif /* CONFIG_4xx */ -#if defined(CFG_GT_6426x) +#if defined(CONFIG_SYS_GT_6426x) unsigned int mirror_hack[16]; #endif #if defined(CONFIG_A3000) || \ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 559d6ea6caa..239924329e6 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1552,6 +1552,13 @@ typedef struct par_io { */ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ +#ifdef CONFIG_MPC8536 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#else +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 +#endif uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ @@ -1572,7 +1579,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ -#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020 +#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ char res2[12]; @@ -1640,37 +1647,37 @@ typedef struct ccsr_gur { #define PORDEVSR_PCI (0x00800000) /* PCI Mode */ -#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) -#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) -#define CFG_MPC85xx_ECM_OFFSET (0x0000) -#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET) -#define CFG_MPC85xx_DDR_OFFSET (0x2000) -#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET) -#define CFG_MPC85xx_DDR2_OFFSET (0x6000) -#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET) -#define CFG_MPC85xx_LBC_OFFSET (0x5000) -#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET) -#define CFG_MPC85xx_PCIX_OFFSET (0x8000) -#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET) -#define CFG_MPC85xx_PCIX2_OFFSET (0x9000) -#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET) -#define CFG_MPC85xx_SATA1_OFFSET (0x18000) -#define CFG_MPC85xx_SATA1_ADDR (CFG_IMMR + CFG_MPC85xx_SATA1_OFFSET) -#define CFG_MPC85xx_SATA2_OFFSET (0x19000) -#define CFG_MPC85xx_SATA2_ADDR (CFG_IMMR + CFG_MPC85xx_SATA2_OFFSET) -#define CFG_MPC85xx_L2_OFFSET (0x20000) -#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET) -#define CFG_MPC85xx_DMA_OFFSET (0x21000) -#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET) -#define CFG_MPC85xx_ESDHC_OFFSET (0x2e000) -#define CFG_MPC85xx_ESDHC_ADDR (CFG_IMMR + CFG_MPC85xx_ESDHC_OFFSET) -#define CFG_MPC85xx_PIC_OFFSET (0x40000) -#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET) -#define CFG_MPC85xx_CPM_OFFSET (0x80000) -#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) -#define CFG_MPC85xx_SERDES1_OFFSET (0xE3000) -#define CFG_MPC85xx_SERDES1_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET) -#define CFG_MPC85xx_SERDES2_OFFSET (0xE3100) -#define CFG_MPC85xx_SERDES2_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) +#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) +#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) +#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) +#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) +#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) +#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) +#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) +#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) +#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) +#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) +#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 03a25c79444..df28c0f2c38 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1348,9 +1348,9 @@ typedef struct immap { extern immap_t *immr; -#define CFG_MPC86xx_DDR_OFFSET (0x2000) -#define CFG_MPC86xx_DDR_ADDR (CFG_IMMR + CFG_MPC86xx_DDR_OFFSET) -#define CFG_MPC86xx_DDR2_OFFSET (0x6000) -#define CFG_MPC86xx_DDR2_ADDR (CFG_IMMR + CFG_MPC86xx_DDR2_OFFSET) +#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET) +#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET) #endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/iopin_8260.h b/include/asm-ppc/iopin_8260.h index 21ed8c2ec0c..619f3a8abea 100644 --- a/include/asm-ppc/iopin_8260.h +++ b/include/asm-ppc/iopin_8260.h @@ -26,140 +26,140 @@ iopin_t; extern __inline__ void iopin_set_high(iopin_t *iopin) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_low(iopin_t *iopin) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_high(iopin_t *iopin) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_low(iopin_t *iopin) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_out(iopin_t *iopin) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_in(iopin_t *iopin) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_out(iopin_t *iopin) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_in(iopin_t *iopin) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_odr(iopin_t *iopin) { - volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_act(iopin_t *iopin) { - volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_odr(iopin_t *iopin) { - volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_act(iopin_t *iopin) { - volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra; + volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_ded(iopin_t *iopin) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_gen(iopin_t *iopin) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_ded(iopin_t *iopin) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_gen(iopin_t *iopin) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_opt2(iopin_t *iopin) { - volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_opt1(iopin_t *iopin) { - volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_opt2(iopin_t *iopin) { - volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_opt1(iopin_t *iopin) { - volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora; + volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h index daddb554d49..0f07ba355e9 100644 --- a/include/asm-ppc/iopin_85xx.h +++ b/include/asm-ppc/iopin_85xx.h @@ -23,121 +23,121 @@ typedef struct { extern __inline__ void iopin_set_high (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_low (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_high (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_low (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_out (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_in (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_out (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_in (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_odr (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_act (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_odr (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_act (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_ded (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_gen (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_ded (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_gen (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } diff --git a/include/asm-ppc/iopin_8xx.h b/include/asm-ppc/iopin_8xx.h index 1946eb24cbd..3a2a682f66c 100644 --- a/include/asm-ppc/iopin_8xx.h +++ b/include/asm-ppc/iopin_8xx.h @@ -46,16 +46,16 @@ extern __inline__ void iopin_set_high(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; *datp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; *datp |= (1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; *datp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; *datp |= (1 << (15 - iopin->pin)); } } @@ -64,16 +64,16 @@ extern __inline__ void iopin_set_low(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; *datp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; *datp &= ~(1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; *datp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; *datp &= ~(1 << (15 - iopin->pin)); } } @@ -82,16 +82,16 @@ extern __inline__ uint iopin_is_high(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; return (*datp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; return (*datp >> (31 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; return (*datp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; return (*datp >> (15 - iopin->pin)) & 1; } return 0; @@ -101,16 +101,16 @@ extern __inline__ uint iopin_is_low(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat; return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat; + volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat; return ((*datp >> (31 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat; return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat; + volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat; return ((*datp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; @@ -120,16 +120,16 @@ extern __inline__ void iopin_set_out(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; *dirp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; *dirp |= (1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; *dirp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; *dirp |= (1 << (15 - iopin->pin)); } } @@ -138,16 +138,16 @@ extern __inline__ void iopin_set_in(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; *dirp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; *dirp &= ~(1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; *dirp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; *dirp &= ~(1 << (15 - iopin->pin)); } } @@ -156,16 +156,16 @@ extern __inline__ uint iopin_is_out(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; return (*dirp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; return (*dirp >> (31 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; return (*dirp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; return (*dirp >> (15 - iopin->pin)) & 1; } return 0; @@ -175,16 +175,16 @@ extern __inline__ uint iopin_is_in(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir; return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir; + volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir; return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir; return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir; + volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir; return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; @@ -194,10 +194,10 @@ extern __inline__ void iopin_set_odr(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; *odrp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; *odrp |= (1 << (31 - iopin->pin)); } } @@ -206,10 +206,10 @@ extern __inline__ void iopin_set_act(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; *odrp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; *odrp &= ~(1 << (31 - iopin->pin)); } } @@ -218,10 +218,10 @@ extern __inline__ uint iopin_is_odr(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; return (*odrp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; return (*odrp >> (31 - iopin->pin)) & 1; } return 0; @@ -231,10 +231,10 @@ extern __inline__ uint iopin_is_act(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr; return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTB) { - volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr; + volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr; return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1; } return 0; @@ -244,16 +244,16 @@ extern __inline__ void iopin_set_ded(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; *parp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; *parp |= (1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; *parp |= (1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; *parp |= (1 << (15 - iopin->pin)); } } @@ -262,16 +262,16 @@ extern __inline__ void iopin_set_gen(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; *parp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; *parp &= ~(1 << (31 - iopin->pin)); } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; *parp &= ~(1 << (15 - iopin->pin)); } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; *parp &= ~(1 << (15 - iopin->pin)); } } @@ -280,16 +280,16 @@ extern __inline__ uint iopin_is_ded(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; return (*parp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; return (*parp >> (31 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; return (*parp >> (15 - iopin->pin)) & 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; return (*parp >> (15 - iopin->pin)) & 1; } return 0; @@ -299,16 +299,16 @@ extern __inline__ uint iopin_is_gen(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar; return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTB) { - volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar; + volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar; return ((*parp >> (31 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTC) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar; return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; } else if (iopin->port == IOPIN_PORTD) { - volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar; + volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar; return ((*parp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; @@ -318,7 +318,7 @@ extern __inline__ void iopin_set_opt2(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; *sorp |= (1 << (15 - iopin->pin)); } } @@ -327,7 +327,7 @@ extern __inline__ void iopin_set_opt1(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; *sorp &= ~(1 << (15 - iopin->pin)); } } @@ -336,7 +336,7 @@ extern __inline__ uint iopin_is_opt2(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; return (*sorp >> (15 - iopin->pin)) & 1; } return 0; @@ -346,7 +346,7 @@ extern __inline__ uint iopin_is_opt1(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso; + volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso; return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; @@ -356,7 +356,7 @@ extern __inline__ void iopin_set_falledge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; *intp |= (1 << (15 - iopin->pin)); } } @@ -365,7 +365,7 @@ extern __inline__ void iopin_set_anyedge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; *intp &= ~(1 << (15 - iopin->pin)); } } @@ -374,7 +374,7 @@ extern __inline__ uint iopin_is_falledge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; return (*intp >> (15 - iopin->pin)) & 1; } return 0; @@ -384,7 +384,7 @@ extern __inline__ uint iopin_is_anyedge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { - volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint; + volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint; return ((*intp >> (15 - iopin->pin)) & 1) ^ 1; } return 0; diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 8efa557972e..98faced366c 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -272,8 +272,11 @@ #define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */ +#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */ #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ @@ -284,8 +287,10 @@ #define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */ #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ diff --git a/include/asm-ppc/status_led.h b/include/asm-ppc/status_led.h index eb81f371c96..037570993ac 100644 --- a/include/asm-ppc/status_led.h +++ b/include/asm-ppc/status_led.h @@ -24,7 +24,7 @@ typedef unsigned long led_id_t; static inline void __led_init (led_id_t mask, int state) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; #ifdef STATUS_LED_PAR immr->STATUS_LED_PAR &= ~mask; @@ -51,12 +51,12 @@ static inline void __led_init (led_id_t mask, int state) static inline void __led_toggle (led_id_t mask) { - ((immap_t *) CFG_IMMR)->STATUS_LED_DAT ^= mask; + ((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask; } static inline void __led_set (led_id_t mask, int state) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; #if (STATUS_LED_ACTIVE == 0) if (state == STATUS_LED_ON) diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 54ac01d3620..74519058414 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -111,6 +111,12 @@ typedef struct bd_info { #ifdef CONFIG_HAS_ETH3 unsigned char bi_enet3addr[6]; #endif +#ifdef CONFIG_HAS_ETH4 + unsigned char bi_enet4addr[6]; +#endif +#ifdef CONFIG_HAS_ETH5 + unsigned char bi_enet5addr[6]; +#endif #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ |