powerpc, 8xx: remove support for 8xx

There was for long time no activity in the 8xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 8xx,
so remove it (with a heavy heart, knowing that I remove
here the root of U-Boot).

Signed-off-by: Heiko Schocher <hs@denx.de>

5 files changed, 0 insertions, 795 deletions

diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 5a6ae0013c1..4c25f6f48f9 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -10,7 +10,6 @@ extra-$(CONFIG_SMC91111)           += smc91111_eeprom
 extra-$(CONFIG_SMC911X)            += smc911x_eeprom
 extra-$(CONFIG_SPI_FLASH_ATMEL)    += atmel_df_pow2
 extra-$(CONFIG_MPC5xxx)            += interrupt
-extra-$(CONFIG_8xx)                += test_burst timer
 extra-$(CONFIG_MPC8260)            += mem_to_mem_idma2intr
 extra-$(CONFIG_PPC)                += sched
 
@@ -29,7 +28,6 @@ COBJS	:= $(ELF:=.o)
 LIB	= $(obj)/libstubs.o
 
 LIBOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o
-LIBOBJS-$(CONFIG_8xx) += test_burst_lib.o
 LIBOBJS-y += stubs.o
 
 .SECONDARY: $(call objectify,$(COBJS))
diff --git a/examples/standalone/test_burst.c b/examples/standalone/test_burst.c
deleted file mode 100644
index f2fdbf19dcb..00000000000
--- a/examples/standalone/test_burst.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * The test exercises SDRAM accesses in burst mode
- */
-
-#include <common.h>
-#include <exports.h>
-
-#include <commproc.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-
-#include <serial.h>
-#include <watchdog.h>
-
-#include "test_burst.h"
-
-/* 8 MB test region of physical RAM */
-#define TEST_PADDR	0x00800000
-/* The uncached virtual region */
-#define TEST_VADDR_NC	0x00800000
-/* The cached virtual region */
-#define TEST_VADDR_C	0x01000000
-/* When an error is detected, the address where the error has been found,
-   and also the current and the expected data will be written to
-   the following flash address
-*/
-#define TEST_FLASH_ADDR	0x40100000
-
-static void test_prepare (void);
-static int test_burst_start (unsigned long size, unsigned long pattern);
-static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
-static int test_mmu_is_on(void);
-static void test_desc(unsigned long size);
-static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern);
-static void signal_init(void);
-static void signal_start(void);
-static void signal_error(void);
-static void test_usage(void);
-
-static unsigned long test_pattern [] = {
-	0x00000000,
-	0xffffffff,
-	0x55555555,
-	0xaaaaaaaa,
-};
-
-
-int test_burst (int argc, char * const argv[])
-{
-	unsigned long size = CACHE_LINE_SIZE;
-	unsigned int pass = 0;
-	int res = 0;
-	int i, j;
-
-	if (argc == 3) {
-		char * d;
-		for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) {
-			size *= 10;
-			size += *d - '0';
-		}
-		if (size == 0 || *d) {
-			test_usage();
-			return 1;
-		}
-		for (d = argv[2]; *d >= '0' && *d <= '9'; d++) {
-			pass *= 10;
-			pass += *d - '0';
-		}
-		if (*d) {
-			test_usage();
-			return 1;
-		}
-	} else if (argc > 3) {
-		test_usage();
-		return 1;
-	}
-
-	size +=  (CACHE_LINE_SIZE - 1);
-	size &= ~(CACHE_LINE_SIZE - 1);
-
-	if (!test_mmu_is_on()) {
-		test_prepare();
-	}
-
-	test_desc(size);
-
-	for (j = 0; !pass || j < pass; j++) {
-		for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]);
-		     i++) {
-			res = test_burst_start(size, test_pattern[i]);
-			if (res != 0) {
-				goto Done;
-			}
-		}
-
-		printf ("Iteration #%d passed\n", j + 1);
-
-		if (tstc() && 0x03 == getc())
-			break;
-	}
-Done:
-	return res;
-}
-
-static void test_prepare (void)
-{
-	printf ("\n");
-
-	caches_init();
-	disable_interrupts();
-	mmu_init();
-
-	printf ("Interrupts are disabled\n");
-	printf ("I-Cache is ON\n");
-	printf ("D-Cache is ON\n");
-	printf ("MMU is ON\n");
-
-	printf ("\n");
-
-	test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0);
-	test_map_8M (TEST_PADDR, TEST_VADDR_C,  1);
-
-	test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0);
-
-	/* Configure GPIO ports */
-	signal_init();
-}
-
-static int test_burst_start (unsigned long size, unsigned long pattern)
-{
-	volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C;
-	volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC;
-	int i, n;
-	int res = 1;
-
-	printf ("Test pattern %08lx ...", pattern);
-
-	n = size / 4;
-
-	for (i = 0; i < n; i ++) {
-		vaddr_c [i] = pattern;
-	}
-	signal_start();
-	flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1);
-
-	for (i = 0; i < n; i ++) {
-		register unsigned long tmp = vaddr_nc [i];
-		if (tmp != pattern) {
-			test_error("2a", vaddr_nc + i, tmp, pattern);
-			goto Done;
-		}
-	}
-
-	for (i = 0; i < n; i ++) {
-		register unsigned long tmp = vaddr_c [i];
-		if (tmp != pattern) {
-			test_error("2b", vaddr_c + i, tmp, pattern);
-			goto Done;
-		}
-	}
-
-	for (i = 0; i < n; i ++) {
-		vaddr_nc [i] = pattern;
-	}
-
-	for (i = 0; i < n; i ++) {
-		register unsigned long tmp = vaddr_nc [i];
-		if (tmp != pattern) {
-			test_error("3a", vaddr_nc + i, tmp, pattern);
-			goto Done;
-		}
-	}
-
-	signal_start();
-	for (i = 0; i < n; i ++) {
-		register unsigned long tmp = vaddr_c [i];
-		if (tmp != pattern) {
-			test_error("3b", vaddr_c + i, tmp, pattern);
-			goto Done;
-		}
-	}
-
-	res = 0;
-Done:
-	printf(" %s\n", res == 0 ? "OK" : "");
-
-	return res;
-}
-
-static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached)
-{
-	mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID);
-	mtspr (MD_TWC, MI_PS8MEG | MI_SVALID);
-	mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2));
-	mtspr (MD_AP, MI_Kp);
-}
-
-static int test_mmu_is_on(void)
-{
-	unsigned long msr;
-
-	asm volatile("mfmsr %0" : "=r" (msr) :);
-
-	return msr & MSR_DR;
-}
-
-static void test_desc(unsigned long size)
-{
-	printf(
-	"The following tests will be conducted:\n"
-	"1)  Map %ld-byte region of physical RAM at 0x%08x\n"
-	"    into two virtual regions:\n"
-	"    one cached at 0x%08x and\n"
-	"    the the other uncached at 0x%08x.\n",
-	size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C);
-
-	puts(
-	"2)  Fill the cached region with a pattern, and flush the cache\n"
-	"2a) Check the uncached region to match the pattern\n"
-	"2b) Check the cached region to match the pattern\n"
-	"3)  Fill the uncached region with a pattern\n"
-	"3a) Check the cached region to match the pattern\n"
-	"3b) Check the uncached region to match the pattern\n"
-	"2b) Change the patterns and go to step 2\n"
-	"\n"
-	);
-}
-
-static void test_error(
-	char * step, volatile void * addr, unsigned long val, unsigned long pattern)
-{
-	volatile unsigned long * p = (void *)TEST_FLASH_ADDR;
-
-	signal_error();
-
-	p[0] = (unsigned long)addr;
-	p[1] = val;
-	p[2] = pattern;
-
-	printf ("\nError at step %s, addr %08lx: read %08lx, pattern %08lx",
-		step, (unsigned long)addr, val, pattern);
-}
-
-static void signal_init(void)
-{
-#if defined(GPIO1_INIT)
-	GPIO1_INIT;
-#endif
-#if defined(GPIO2_INIT)
-	GPIO2_INIT;
-#endif
-}
-
-static void signal_start(void)
-{
-#if defined(GPIO1_INIT)
-	if (GPIO1_DAT & GPIO1_BIT) {
-		GPIO1_DAT &= ~GPIO1_BIT;
-	} else {
-		GPIO1_DAT |= GPIO1_BIT;
-	}
-#endif
-}
-
-static void signal_error(void)
-{
-#if defined(GPIO2_INIT)
-	if (GPIO2_DAT & GPIO2_BIT) {
-		GPIO2_DAT &= ~GPIO2_BIT;
-	} else {
-		GPIO2_DAT |= GPIO2_BIT;
-	}
-#endif
-}
-
-static void test_usage(void)
-{
-	printf("Usage: go 0x40004 [size] [count]\n");
-}
diff --git a/examples/standalone/test_burst.h b/examples/standalone/test_burst.h
deleted file mode 100644
index 87f5927a8e9..00000000000
--- a/examples/standalone/test_burst.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _TEST_BURST_H
-#define _TEST_BURST_H
-
-/* Cache line size */
-#define CACHE_LINE_SIZE		16
-/* Binary logarithm of the cache line size */
-#define LG_CACHE_LINE_SIZE	4
-
-#ifndef __ASSEMBLY__
-extern void mmu_init(void);
-extern void caches_init(void);
-extern void flush_dcache_range(unsigned long start, unsigned long stop);
-#endif
-
-#endif /* _TEST_BURST_H */
diff --git a/examples/standalone/test_burst_lib.S b/examples/standalone/test_burst_lib.S
deleted file mode 100644
index fd3256e88b9..00000000000
--- a/examples/standalone/test_burst_lib.S
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include "test_burst.h"
-
-	.text
-/*
- *	void mmu_init(void);
- *
- *	This function turns the MMU on
- *
- *	Three 8 MByte regions are mapped 1:1, uncached
- *	- SDRAM lower 8 MByte
- *	- SDRAM higher 8 MByte
- *	- IMMR
- */
-	.global mmu_init
-mmu_init:
-	tlbia			/* Invalidate all TLB entries */
-	li	r8, 0
-	mtspr	MI_CTR, r8	/* Set instruction control to zero */
-	lis	r8, MD_RESETVAL@h
-	mtspr	MD_CTR, r8	/* Set data TLB control */
-
-	/* Now map the lower 8 Meg into the TLBs.  For this quick hack,
-	 * we can load the instruction and data TLB registers with the
-	 * same values.
-	 */
-	li	r8, MI_EVALID		/* Create EPN for address 0 */
-	mtspr	MI_EPN, r8
-	mtspr	MD_EPN, r8
-	li	r8, MI_PS8MEG		/* Set 8M byte page */
-	ori	r8, r8, MI_SVALID	/* Make it valid */
-	mtspr	MI_TWC, r8
-	mtspr	MD_TWC, r8
-	li	r8, MI_BOOTINIT|0x2	/* Create RPN for address 0 */
-	mtspr	MI_RPN, r8		/* Store TLB entry */
-	mtspr	MD_RPN, r8
-	lis	r8, MI_Kp@h		/* Set the protection mode */
-	mtspr	MI_AP, r8
-	mtspr	MD_AP, r8
-
-	/* Now map the higher 8 Meg into the TLBs.  For this quick hack,
-	 * we can load the instruction and data TLB registers with the
-	 * same values.
-	 */
-	lwz	r9,20(r2)		/* gd->ram_size */
-	addis	r9,r9,-0x80
-
-	mr	r8, r9			/* Higher 8 Meg in SDRAM */
-	ori	r8, r8, MI_EVALID	/* Mark page valid */
-	mtspr	MI_EPN, r8
-	mtspr	MD_EPN, r8
-	li	r8, MI_PS8MEG		/* Set 8M byte page */
-	ori	r8, r8, MI_SVALID	/* Make it valid */
-	mtspr	MI_TWC, r8
-	mtspr	MD_TWC, r8
-	mr	r8, r9
-	ori	r8, r8, MI_BOOTINIT|0x2
-	mtspr	MI_RPN, r8		/* Store TLB entry */
-	mtspr	MD_RPN, r8
-	lis	r8, MI_Kp@h		/* Set the protection mode */
-	mtspr	MI_AP, r8
-	mtspr	MD_AP, r8
-
-	/* Map another 8 MByte at the IMMR to get the processor
-	 * internal registers (among other things).
-	 */
-	mfspr	r9, 638			/* Get current IMMR */
-	andis.	r9, r9, 0xff80		/* Get 8Mbyte boundary */
-
-	mr	r8, r9			/* Create vaddr for TLB */
-	ori	r8, r8, MD_EVALID	/* Mark it valid */
-	mtspr	MD_EPN, r8
-	li	r8, MD_PS8MEG		/* Set 8M byte page */
-	ori	r8, r8, MD_SVALID	/* Make it valid */
-	mtspr	MD_TWC, r8
-	mr	r8, r9			/* Create paddr for TLB */
-	ori	r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
-	mtspr	MD_RPN, r8
-
-	/* We now have the lower and higher 8 Meg mapped into TLB entries,
-	 * and the caches ready to work.
-	 */
-	mfmsr	r0
-	ori	r0,r0,MSR_DR|MSR_IR
-	mtspr	SRR1,r0
-	mflr	r0
-	mtspr	SRR0,r0
-	SYNC
-	rfi	/* enables MMU */
-
-/*
- *	void caches_init(void);
- */
-	.globl	caches_init
-caches_init:
-	sync
-
-	mfspr	r3, IC_CST		/* Clear error bits */
-	mfspr	r3, DC_CST
-
-	lis	r3, IDC_UNALL@h		/* Unlock all */
-	mtspr	IC_CST, r3
-	mtspr	DC_CST, r3
-
-	lis	r3, IDC_INVALL@h	/* Invalidate all */
-	mtspr	IC_CST, r3
-	mtspr	DC_CST, r3
-
-	lis	r3, IDC_ENABLE@h	/* Enable all */
-	mtspr	IC_CST, r3
-	mtspr	DC_CST, r3
-
-	blr
-
-/*
- *	void flush_dcache_range(unsigned long start, unsigned long stop);
- */
-	.global flush_dcache_range
-flush_dcache_range:
-	li	r5,CACHE_LINE_SIZE-1
-	andc	r3,r3,r5
-	subf	r4,r3,r4
-	add	r4,r4,r5
-	srwi.	r4,r4,LG_CACHE_LINE_SIZE
-	beqlr
-	mtctr	r4
-
-1:	dcbf	0,r3
-	addi	r3,r3,CACHE_LINE_SIZE
-	bdnz	1b
-	sync				/* wait for dcbf's to get to ram */
-	blr
-
-/*
- *	void disable_interrupts(void);
- */
-	.global disable_interrupts
-disable_interrupts:
-	mfmsr	r0
-	rlwinm	r0,r0,0,17,15
-	mtmsr	r0
-	blr
diff --git a/examples/standalone/timer.c b/examples/standalone/timer.c
deleted file mode 100644
index dbd5c16f97f..00000000000
--- a/examples/standalone/timer.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <mpc8xx_irq.h>
-#include <exports.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef	DEBUG
-
-#define	TIMER_PERIOD	1000000		/* 1 second clock */
-
-static void timer_handler (void *arg);
-
-
-/* Access functions for the Machine State Register */
-static __inline__ unsigned long get_msr(void)
-{
-    unsigned long msr;
-
-    asm volatile("mfmsr %0" : "=r" (msr) :);
-    return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
-    asm volatile("mtmsr %0" : : "r" (msr));
-}
-
-/*
- * Definitions to access the CPM Timer registers
- * See 8xx_immap.h for Internal Memory Map layout,
- * and commproc.h for CPM Interrupt vectors (aka "IRQ"s)
- */
-
-typedef struct tid_8xx_cpmtimer_s {
-  int		 cpm_vec;	/* CPM Interrupt Vector for this timer	*/
-  ushort	*tgcrp;		/* Pointer to Timer Global Config Reg.	*/
-  ushort	*tmrp;		/* Pointer to Timer Mode Register	*/
-  ushort	*trrp;		/* Pointer to Timer Reference Register	*/
-  ushort	*tcrp;		/* Pointer to Timer Capture Register	*/
-  ushort	*tcnp;		/* Pointer to Timer Counter Register	*/
-  ushort	*terp;		/* Pointer to Timer Event Register	*/
-} tid_8xx_cpmtimer_t;
-
-#ifndef CLOCKRATE
-#  define CLOCKRATE 64
-#endif
-
-#define	CPMT_CLOCK_DIV		16
-#define	CPMT_MAX_PRESCALER	256
-#define CPMT_MAX_REFERENCE	65535	/* max. unsigned short */
-
-#define	CPMT_MAX_TICKS		(CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER)
-#define	CPMT_MAX_TICKS_WITH_DIV	(CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER * CPMT_CLOCK_DIV)
-#define	CPMT_MAX_INTERVAL	(CPMT_MAX_TICKS_WITH_DIV / CLOCKRATE)
-
-/* For now: always use max. prescaler value */
-#define	CPMT_PRESCALER		(CPMT_MAX_PRESCALER)
-
-/* CPM Timer Event Register Bits */
-#define	CPMT_EVENT_CAP		0x0001	/* Capture Event		*/
-#define	CPMT_EVENT_REF		0x0002	/* Reference Counter Event	*/
-
-/* CPM Timer Global Config Register */
-#define	CPMT_GCR_RST		0x0001	/* Reset  Timer			*/
-#define	CPMT_GCR_STP		0x0002	/* Stop   Timer			*/
-#define	CPMT_GCR_FRZ		0x0004	/* Freeze Timer			*/
-#define	CPMT_GCR_GM_CAS		0x0008	/* Gate Mode / Cascade Timers	*/
-#define	CPMT_GCR_MASK		(CPMT_GCR_RST|CPMT_GCR_STP|CPMT_GCR_FRZ|CPMT_GCR_GM_CAS)
-
-/* CPM Timer Mode register */
-#define	CPMT_MR_GE		0x0001	/* Gate Enable			*/
-#define	CPMT_MR_ICLK_CASC	0x0000	/* Clock internally cascaded	*/
-#define	CPMT_MR_ICLK_CLK	0x0002	/* Clock = system clock		*/
-#define	CPMT_MR_ICLK_CLKDIV	0x0004	/* Clock = system clock / 16	*/
-#define	CPMT_MR_ICLK_TIN	0x0006	/* Clock = TINx signal		*/
-#define	CPMT_MR_FRR		0x0008	/* Free Run / Restart		*/
-#define	CPMT_MR_ORI		0x0010	/* Out. Reference Interrupt En.	*/
-#define	CPMT_MR_OM		0x0020	/* Output Mode			*/
-#define	CPMT_MR_CE_DIS		0x0000	/* Capture/Interrupt disabled	*/
-#define	CPMT_MR_CE_RISE		0x0040	/* Capt./Interr. on rising  TIN	*/
-#define CPMT_MR_CE_FALL		0x0080	/* Capt./Interr. on falling TIN	*/
-#define	CPMT_MR_CE_ANY		0x00C0	/* Capt./Interr. on any TIN edge*/
-
-
-/*
- * which CPM timer to use - index starts at 0 (= timer 1)
- */
-#define	TID_TIMER_ID	0	/* use CPM timer 1		*/
-
-void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval);
-
-static const char usage[] = "\n[q, b, e, ?] ";
-
-int timer (int argc, char * const argv[])
-{
-	cpmtimer8xx_t *cpmtimerp;	/* Pointer to the CPM Timer structure   */
-	tid_8xx_cpmtimer_t hw;
-	tid_8xx_cpmtimer_t *hwp = &hw;
-	int c;
-	int running;
-
-	app_startup(argv);
-
-	/* Pointer to CPM Timer structure */
-	cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer;
-
-	printf ("TIMERS=0x%x\n", (unsigned) cpmtimerp);
-
-	/* Initialize pointers depending on which timer we use */
-	switch (TID_TIMER_ID) {
-	case 0:
-		hwp->tmrp = &(cpmtimerp->cpmt_tmr1);
-		hwp->trrp = &(cpmtimerp->cpmt_trr1);
-		hwp->tcrp = &(cpmtimerp->cpmt_tcr1);
-		hwp->tcnp = &(cpmtimerp->cpmt_tcn1);
-		hwp->terp = &(cpmtimerp->cpmt_ter1);
-		hwp->cpm_vec = CPMVEC_TIMER1;
-		break;
-	case 1:
-		hwp->tmrp = &(cpmtimerp->cpmt_tmr2);
-		hwp->trrp = &(cpmtimerp->cpmt_trr2);
-		hwp->tcrp = &(cpmtimerp->cpmt_tcr2);
-		hwp->tcnp = &(cpmtimerp->cpmt_tcn2);
-		hwp->terp = &(cpmtimerp->cpmt_ter2);
-		hwp->cpm_vec = CPMVEC_TIMER2;
-		break;
-	case 2:
-		hwp->tmrp = &(cpmtimerp->cpmt_tmr3);
-		hwp->trrp = &(cpmtimerp->cpmt_trr3);
-		hwp->tcrp = &(cpmtimerp->cpmt_tcr3);
-		hwp->tcnp = &(cpmtimerp->cpmt_tcn3);
-		hwp->terp = &(cpmtimerp->cpmt_ter3);
-		hwp->cpm_vec = CPMVEC_TIMER3;
-		break;
-	case 3:
-		hwp->tmrp = &(cpmtimerp->cpmt_tmr4);
-		hwp->trrp = &(cpmtimerp->cpmt_trr4);
-		hwp->tcrp = &(cpmtimerp->cpmt_tcr4);
-		hwp->tcnp = &(cpmtimerp->cpmt_tcn4);
-		hwp->terp = &(cpmtimerp->cpmt_ter4);
-		hwp->cpm_vec = CPMVEC_TIMER4;
-		break;
-	}
-
-	hwp->tgcrp = &cpmtimerp->cpmt_tgcr;
-
-	printf ("Using timer %d\n"
-			"tgcr @ 0x%x, tmr @ 0x%x, trr @ 0x%x,"
-			" tcr @ 0x%x, tcn @ 0x%x, ter @ 0x%x\n",
-			TID_TIMER_ID + 1,
-			(unsigned) hwp->tgcrp,
-			(unsigned) hwp->tmrp,
-			(unsigned) hwp->trrp,
-			(unsigned) hwp->tcrp,
-			(unsigned) hwp->tcnp,
-			(unsigned) hwp->terp
-			);
-
-	/* reset timer    */
-	*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
-
-	/* clear all events */
-	*hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF);
-
-	puts(usage);
-	running = 0;
-	while ((c = getc()) != 'q') {
-	    if (c == 'b') {
-
-		setPeriod (hwp, TIMER_PERIOD);	/* Set period and start ticking */
-
-		/* Install interrupt handler (enable timer in CIMR) */
-		install_hdlr (hwp->cpm_vec, timer_handler, hwp);
-
-		printf ("Enabling timer\n");
-
-		/* enable timer */
-		*hwp->tgcrp |= (CPMT_GCR_RST << TID_TIMER_ID);
-		running = 1;
-
-#ifdef	DEBUG
-		printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
-			" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
-				*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
-				*hwp->tcrp,  *hwp->tcnp, *hwp->terp
-				);
-#endif
-	    } else if (c == 'e') {
-
-		printf ("Stopping timer\n");
-
-		*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
-		running = 0;
-
-#ifdef	DEBUG
-		printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
-			" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
-				*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
-				*hwp->tcrp,  *hwp->tcnp, *hwp->terp
-			);
-#endif
-		/* Uninstall interrupt handler */
-		free_hdlr (hwp->cpm_vec);
-
-	    } else if (c == '?') {
-#ifdef	DEBUG
-		cpic8xx_t *cpm_icp = &((immap_t *) gd->bd->bi_immr_base)->im_cpic;
-		sysconf8xx_t *siup = &((immap_t *) gd->bd->bi_immr_base)->im_siu_conf;
-#endif
-
-		printf ("\ntgcr=0x%x, tmr=0x%x, trr=0x%x,"
-			" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
-				*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
-				*hwp->tcrp,  *hwp->tcnp, *hwp->terp
-			);
-#ifdef	DEBUG
-		printf ("SIUMCR=0x%08lx, SYPCR=0x%08lx,"
-			" SIMASK=0x%08lx, SIPEND=0x%08lx\n",
-				siup->sc_siumcr,
-				siup->sc_sypcr,
-				siup->sc_simask,
-				siup->sc_sipend
-			);
-
-		printf ("CIMR=0x%08lx, CICR=0x%08lx, CIPR=0x%08lx\n",
-			cpm_icp->cpic_cimr,
-			cpm_icp->cpic_cicr,
-			cpm_icp->cpic_cipr
-			);
-#endif
-	    } else {
-		printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n");
-	    }
-	    puts(usage);
-	}
-	if (running) {
-		printf ("Stopping timer\n");
-		*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
-		free_hdlr (hwp->cpm_vec);
-	}
-
-	return (0);
-}
-
-
-/* Set period in microseconds and start.
- * Truncate to maximum period if more than this is requested - but warn about it.
- */
-
-void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval)
-{
-	unsigned short prescaler;
-	unsigned long ticks;
-
-	printf ("Set interval %ld us\n", interval);
-
-	/* Warn if requesting longer period than possible */
-	if (interval > CPMT_MAX_INTERVAL) {
-		printf ("Truncate interval %ld to maximum (%d)\n",
-				interval, CPMT_MAX_INTERVAL);
-		interval = CPMT_MAX_INTERVAL;
-	}
-	/*
-	 * Check if we want to use clock divider:
-	 * Since the reference counter can be incremented only in integer steps,
-	 * we try to keep it as big as possible to allow the resulting period to be
-	 * as precise as possible.
-	 */
-	/* prescaler, enable interrupt, restart after ref count is reached */
-	prescaler = (ushort) ((CPMT_PRESCALER - 1) << 8) |
-			CPMT_MR_ORI |
-			CPMT_MR_FRR;
-
-	ticks = ((ulong) CLOCKRATE * interval);
-
-	if (ticks > CPMT_MAX_TICKS) {
-		ticks /= CPMT_CLOCK_DIV;
-		prescaler |= CPMT_MR_ICLK_CLKDIV;	/* use system clock divided by 16 */
-	} else {
-		prescaler |= CPMT_MR_ICLK_CLK;	/* use system clock without divider */
-	}
-
-#ifdef	DEBUG
-	printf ("clock/%d, prescale factor %d, reference %ld, ticks %ld\n",
-			(ticks > CPMT_MAX_TICKS) ? CPMT_CLOCK_DIV : 1,
-			CPMT_PRESCALER,
-			(ticks / CPMT_PRESCALER),
-			ticks
-			);
-#endif
-
-	/* set prescaler register */
-	*hwp->tmrp = prescaler;
-
-	/* clear timer counter */
-	*hwp->tcnp = 0;
-
-	/* set reference register */
-	*hwp->trrp = (unsigned short) (ticks / CPMT_PRESCALER);
-
-#ifdef	DEBUG
-	printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
-		" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
-			*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
-			*hwp->tcrp,  *hwp->tcnp, *hwp->terp
-		);
-#endif
-}
-
-/*
- * Handler for CPMVEC_TIMER1 interrupt
- */
-static
-void timer_handler (void *arg)
-{
-	tid_8xx_cpmtimer_t *hwp = (tid_8xx_cpmtimer_t *)arg;
-
-	/* printf ("** TER1=%04x ** ", *hwp->terp); */
-
-	/* just for demonstration */
-	printf (".");
-
-	/* clear all possible events: Ref. and Cap. */
-	*hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF);
-}