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| author | Hari Nagalla <hnagalla@ti.com> | 2023-05-31 00:56:01 -0500 |
|---|---|---|
| committer | Udit Kumar <u-kumar1@ti.com> | 2023-05-31 16:21:19 +0530 |
| commit | 1ccd1ab3ba9d738180ceff7f3d411dc9be055027 (patch) | |
| tree | d9a08ac755e8916fddcc7d31416bae8c06ffb4ea /examples | |
| parent | faa4ecc1273057b8aef884bb7f1486b7dbfc732d (diff) | |
arm: dts: k3-j721s2-main: Add R5F and C7x DSP Remote processor nodes
The J721S2 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters in MAIN voltage domain. Each of these can be
configured at boot time to be either run in a LockStep mode or in an
Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). The TCMs of both Cores are
combined in LockStep-mode to provide a larger 128 KB of memory, but
otherwise are functionally similar to those on J721E SoCs.
Add the DT nodes for the MAIN domain R5F cluster/subsystems, the two
R5F cores are added as child nodes to each of the R5F cluster nodes.
The clusters are configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR
with boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
MAIN R5FSS0 Core0: j721s2-main-r5f0_0-fw (both in LockStep & Split modes)
MAIN R5FSS0 Core1: j721s2-main-r5f0_1-fw (needed only in Split mode)
MAIN R5FSS1 Core0: j721s2-main-r5f1_0-fw (both in LockStep & Split modes)
MAIN R5FSS1 Core1: j721s2-main-r5f1_1-fw (needed only in Split mode)
The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain. The
C71x DSPs are 64 bit machine with fixed and floating point DSP operations.
Similar to the R5F remote cores, the inter-processor communication
between the main A72 cores and these DSP cores is achieved through
shared memory and Mailboxes.
The following firmware names are used by default for these DSP cores,
and can be overridden in a board dts file if desired:
MAIN C71_0 : j721s2-c71_0-fw
MAIN C71_1 : j721s2-c71_1-fw
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Diffstat (limited to 'examples')
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