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authorYork Sun <yorksun@freescale.com>2013-10-28 16:36:02 -0700
committerYork Sun <yorksun@freescale.com>2013-11-25 11:43:47 -0800
commit00ec3fd21170e463e29723976d37f8ea2316f168 (patch)
tree6ff134a140dd253ec4bc925fad27200bece2fdca /drivers
parentd4263b8adb5bd940c95cbaebaa0da9eaf759bfed (diff)
Driver/DDR: Update DDR driver to allow non-zero base address
The DRAM base has been zero for Power SoCs. It could be non-zero for ARM SoCs. Use a macro instead of hard-coding to zero. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ddr/fsl/main.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index b4988e194cf..d0cd58925c3 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -255,7 +255,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
}
- current_mem_base = 0ull;
+ current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
total_mem = 0;
if (pinfo->memctl_opts[0].memctl_interleaving) {
rank_density = pinfo->dimm_params[0][0].rank_density >>
@@ -535,8 +535,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
}
}
- total_mem = 1 + (((unsigned long long)max_end << 24ULL)
- | 0xFFFFFFULL);
+ total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
+ 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
}
return total_mem;