diff options
| author | Santhosh Kumar K <s-k6@ti.com> | 2024-02-14 16:27:46 +0530 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2024-03-21 14:26:33 +0000 |
| commit | a410d435a054851c94ebdfe2815f2ea90a4d949a (patch) | |
| tree | 1a1eea5ee37a7e5f1d3abf7a7f71bba86989c7dd /drivers | |
| parent | 989440c887c8eb01e84f0b371527f64b7e04f323 (diff) | |
ram: k3-ddrss: Setup ECC region start and range
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ram/k3-ddrss/k3-ddrss.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index c6a62785bd..b34f645396 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -122,8 +122,8 @@ struct k3_msmc { #define K3_DDRSS_MAX_ECC_REGIONS 3 struct k3_ddrss_ecc_region { - u32 start; - u32 range; + u64 start; + u64 range; }; struct k3_ddrss_desc { @@ -555,7 +555,7 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss) } } -static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size) +static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size) { writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG); writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); @@ -731,13 +731,13 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) { - u32 ecc_region_start = ddrss->ecc_regions[0].start; - u32 ecc_range = ddrss->ecc_regions[0].range; + u64 ecc_region_start = ddrss->ecc_regions[0].start; + u64 ecc_range = ddrss->ecc_regions[0].range; u32 base = (u32)ddrss->ddrss_ss_cfg; u32 val; /* Only Program region 0 which covers full ddr space */ - k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range); + k3_ddrss_set_ecc_range_r0(base, ecc_region_start - ddrss->ddr_bank_base[0], ecc_range); /* Enable ECC, RMW, WR_ALLOC */ writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | @@ -803,8 +803,8 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss); /* Always configure one region that covers full DDR space */ - ddrss->ecc_regions[0].start = gd->ram_base; - ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space; + ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0]; + ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space; k3_ddrss_lpddr4_ecc_init(ddrss); } |