diff options
| author | Bryan Brattlof <bb@ti.com> | 2023-07-17 17:15:26 -0500 |
|---|---|---|
| committer | Praneeth Bajjuri <praneeth@ti.com> | 2023-11-28 11:36:12 -0600 |
| commit | 77053f97e011df8fa2d3f098f43bda3c2d7facd6 (patch) | |
| tree | 9bdd5e3b6561dc021ae3863c441bc28f06ab05be /drivers | |
| parent | 71b8c840ca61a4e11b2cdf63b0e6580ecb427912 (diff) | |
ram: k3-ddrss: do not touch ctrl regs during training
commit af7c33c103450e06aecf8adba8cbc8c522295be1 upstream.
During LPDDR initialization we will loop through a series of frequency
changes in order to train at the various operating frequencies. During
this training, accessing the DRAM_CLASS bitfield could happen during a
frequency change and cause the read to hang.
Store the DRAM type into the main structure to avoid multiple readings
while the independent phy is training.
Signed-off-by: Bryan Brattlof <bb@ti.com>
[praneeth@ti.com: cherrypick from v2023.10]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ram/k3-ddrss/k3-ddrss.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 75d13df8ad..28129d52a6 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -138,6 +138,7 @@ struct k3_ddrss_desc { u32 ddr_freq1; u32 ddr_freq2; u32 ddr_fhs_cnt; + u32 dram_class; struct udevice *vtt_supply; u32 instance; lpddr4_obj *driverdt; @@ -243,14 +244,11 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss) static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) { - u32 dram_class; struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); - dram_class = k3_lpddr4_read_ddr_type(pd); - - switch (dram_class) { + switch (ddrss->dram_class) { case DENALI_CTL_0_DRAM_CLASS_DDR4: break; case DENALI_CTL_0_DRAM_CLASS_LPDDR4: @@ -263,13 +261,12 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) { - u32 dram_class; int ret; lpddr4_privatedata *pd = &ddrss->pd; - dram_class = k3_lpddr4_read_ddr_type(pd); + ddrss->dram_class = k3_lpddr4_read_ddr_type(pd); - switch (dram_class) { + switch (ddrss->dram_class) { case DENALI_CTL_0_DRAM_CLASS_DDR4: /* Set to ddr_freq1 from DT for DDR4 */ ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); |